A Growing Group Of Diverse
AI
SeniorDigital/MemoryMaskDesignEngineer
“Senior Digital/Memory Mask Design Engineer at A Growing Group Of Diverse. Skills: Memory Mask Design, IC layout, advanced CMOS process nodes, physical verification. Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry standard methodologies. Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, an”
What You'll Achieve.
influencing project direction; ensuring alignment with organizational objectives
Industry & Context.
identification and resolution of complex physical design issues
What They're Looking For.
Must Have
6+ Years of proven experience in Memory layout in advanced CMOS process, Detailed knowledge of industry standard EDA tools for Cadence, Experience with layout of high-performance memories of various types, Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding), Experience with floor planning, block level routing and macro level assembly, Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.
What You'll Do.
Implement IC layout of innovative
high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm
7nm and lower nodes following industry standard methodologies
Lead the architecture and layout design of key memory subsystems
including control logic
and decoders for advanced technology nodes
Direct custom layout and verification of complex memory cells
setting standards and methodologies for compiler-driven design flows
Be responsible for and optimize all physical verification activities
and comprehensive tape-out checks
Drive the identification and resolution of complex physical design issues in compiler-generated layouts
mentoring junior engineers in established methodologies
Provide guidance on IR drop and mitigation strategies
establishing design methodologies for robust memory layouts
Possess deep expertise in ultra-deep sub-micron layout challenges
regularly innovating and implementing advanced solutions
Development of memory compilers
leading solving efforts and driving optimization for performance
and manufacturability
How You'll Work.
Team & Collaboration
Cultivate effective teamwork across multi-functional teams; representing the team in technical discussions with customers
Applying for this Senior Digital/Memory Mask Design Engineer role?
Most applicants get filtered before a human reads their resume. See if yours makes the cut.
How to Apply on Workday
- Workday has a multi-step form — save your progress after every section.
- "Apply With LinkedIn" can fail or lose data; manual entry is more reliable.
- Watch for the "Submit for Review" final step — hitting "Save" alone does not submit.
- Job requisition numbers are useful when following up with HR by email.
ANONYMOUS · UNFILTERED
What do employees actually say about A Growing Group Of Diverse?
Real rants from real employees. Read before you apply.