NVIDIA

Technology

SeniorDigitalDesignEngineer

$136–265k Santa Clara, California, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior Digital Design Engineer at NVIDIA. Skills: Digital design, AI infrastructure, Connectivity protocols. Analyze architectural requirements. Perform trade-off analysis”

Industry & Context.

Technology
Problems you'll solve

Analytical skills

What They're Looking For.

Must Have

Bachelors or Master's Degree, 5+ years relevant work experience, Experience with high-speed connectivity protocols, Proven track record of delivering high bandwidth datapath blocks, Deep understanding of ASIC design flows

Nice to Have

Master's Degree

What You'll Do.

Analyze architectural requirements

Perform trade-off analysis

Deliver high performance RTL Blocks

Deliver area efficient RTL Blocks

Deliver power efficient RTL Blocks

Craft micro-architecture specification

Implement high-quality RTL

Deliver verified block

Deliver synthesis clean block

Deliver timing clean block

Identify potential IP solutions

Assist in selecting IP solutions

Assist in customizing IP solutions

Assist in integrating IP solutions

How You'll Work.

Team & Collaboration

Chip architects; Verification engineers; Formal verification engineers; SoC integration engineers

Full Job Description

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working engineers crafting and implementing NVLink Fusion based AI infrastructure System-on-Chips. You will get a chance to create real impact in a dynamic, industry leading, technology-focused company, while working on NVLink Fusion technology. NVLink Fusion is the enabler for the next generation of standardized rack-scale AI connectivity. **What you 'll be doing:** * As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. * Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean block. * Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers in order to meet the goals of the block in a timely manner * Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions. **What we need to see:** * Bachelors or Master's Degree, or equivalent experience in Electrical Engineering or Computer Engineering * 5+ years of relevant work experience. * Experience working with high-speed connectivity protocols such as NVLink, PCI-Express, Ethernet, UCIE etc. * Proven track record of delivering high bandwidth datapath blocks such as data movers, protocol adaptors, network-on-chip, arbiters and schedulers etc. * Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal skills, excellent teammate With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us, and,

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