Analog Devices
Semiconductor
SeniorDFTEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Senior DFT Engineer at Analog Devices. Skills: DFT, ATPG, Test Compression, MBIST. Develop DFT specifications. Develop DFT architecture”
What You'll Achieve.
High Coverage; Low Power; Low Test Time; High quality patterns
Industry & Context.
Failure analysis debug; Diagnosis
10% travel
What They're Looking For.
Must Have
6 - 8 years ASIC/SoC DFT experience, Expert DFT architecture knowledge, Expert Scan knowledge, Expert Test Compression knowledge, Expert At-Speed Test knowledge, Expert MBIST knowledge, Expert LBIST knowledge, Hands-on Scan Insertion experience, Hands-on Compression Insertion experience, Hands-on On-Chip Clock Control Insertion experience, Hands-on ATPG experience, Hands-on DFT Verification experience, Gate-level simulation with SDF experience, Silicon test bring up support experience, Failure analysis debug/diagnosis experience, Perl/Python/Tcl scripting experience
Nice to Have
Cadence DFT tools experience, Synopsys DFT tools experience, IEEE 1149 experience, JTAG experience, Static Timing Analysis experience, Built-In Self-Test experience, Synthesis and DFT Insertion experience, Low Power Scan experience, UPF experience
What You'll Do.
Develop DFT specifications
Develop DFT architecture
Provide methodology support
Support product lines
Deliver ATPG patterns
Perform Pre/Post silicon verification
Mentor junior team members
How You'll Work.
Team & Collaboration
Relationships with peer-organizations
Communication Scope
Written communication; Verbal communication
Full Job Description
**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). Job Description * DFT specifications, architecture and implementation using state-of-the-art methodologies and tools * Methodology support, DFT Flow Automation, and DFT Innovation * Support all product lines with High Coverage, Low Power, Low Test Time * Deliver high quality, verified, Automatic Test Pattern Generation (ATPG) patterns * Pre/Post silicon verification & debug * Work independently and mentor junior team members Minimum Qualifications * 6 - 8 years of directly related experience in ASIC/SoC DFT * Expert level knowledge of DFT architecture and planning * Hands on Tessent DFT Tool experience * Expert level knowledge of Scan, Test Compression, At-Speed Test, Memory Built-In Self-Test (MBIST), Logic Bist (LBIST) * Hands-on experience of Scan Insertion, Compression Insertion, On-Chip Clock Control Insertion, ATPG, DFT Verification * Gate-level simulation with SDF * Silicon test bring up support, failure analysis debug/diagnosis * Scripting: Perl/Python/Tcl * Team-player: the ability to forge and maintain relationships with peer-organizations * Strong written and verbal communication skills Preferred Qualifications * Experience with Cadence and Synopsys DFT tools * Experience with IEEE 1149 and JTAG * Experience wit
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