Analog Devices, Inc.
semiconductor
SeniorDFTEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Senior DFT Engineer at Analog Devices, Inc.. Skills: ASIC/SoC DFT, DFT architecture, Tessent DFT Tool, ATPG. DFT specifications, architecture and implementation. Methodology support, DFT Flow Automation”
What You'll Achieve.
High Coverage; Low Power; Low Test Time; Deliver high quality, verified, Automatic Test Pattern Generation (ATPG) patterns
Industry & Context.
failure analysis debug/diagnosis
Travel: Yes, 10% of the time
What They're Looking For.
Must Have
6 - 8 years of directly related experience in ASIC/SoC DFT, Expert level knowledge of DFT architecture and planning, Hands on Tessent DFT Tool experience, Expert level knowledge of Scan, Test Compression, At-Speed Test, Memory Built-In Self-Test (MBIST), Logic Bist (LBIST), Hands-on experience of Scan Insertion, Compression Insertion, On-Chip Clock Control Insertion, ATPG, DFT Verification, Gate-level simulation with SDF, Silicon test bring up support, failure analysis debug/diagnosis, Scripting: Perl/Python/Tcl, Team-player: the ability to forge and maintain relationships with peer-organizations, written and verbal communication skills
Nice to Have
Experience with Cadence and Synopsys DFT tools, Experience with IEEE 1149 and JTAG, Experience with Static Timing Analysis, Experience with Built-In Self-Test (BIST), Experience with Synthesis and DFT Insertion, Experience with Low Power Scan and UPF
What You'll Do.
architecture and implementation
Support product lines
Deliver ATPG patterns
Pre/Post silicon verification & debug
Mentor junior team members
How You'll Work.
Team & Collaboration
Work independently and mentor junior team members; forge and maintain relationships with peer-organizations
Communication Scope
written and verbal communication skills
Full Job Description
**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). Job Description * DFT specifications, architecture and implementation using state-of-the-art methodologies and tools * Methodology support, DFT Flow Automation, and DFT Innovation * Support all product lines with High Coverage, Low Power, Low Test Time * Deliver high quality, verified, Automatic Test Pattern Generation (ATPG) patterns * Pre/Post silicon verification & debug * Work independently and mentor junior team members Minimum Qualifications * 6 - 8 years of directly related experience in ASIC/SoC DFT * Expert level knowledge of DFT architecture and planning * Hands on Tessent DFT Tool experience * Expert level knowledge of Scan, Test Compression, At-Speed Test, Memory Built-In Self-Test (MBIST), Logic Bist (LBIST) * Hands-on experience of Scan Insertion, Compression Insertion, On-Chip Clock Control Insertion, ATPG, DFT Verification * Gate-level simulation with SDF * Silicon test bring up support, failure analysis debug/diagnosis * Scripting: Perl/Python/Tcl * Team-player: the ability to forge and maintain relationships with peer-organizations * Strong written and verbal communication skills Preferred Qualifications * Experience with Cadence and Synopsys DFT tools * Experience with IEEE 1149 and JTAG * Experience wit
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