SeniorDesignVerificationEngineer

## Accountabilities Define and execute comprehensive design verification strategies for ASIC and FPGA systems, ensuring functional correctness, performance validation, and coverage closure across complex designs. Develop and maintain advanced SystemVerilog/UVM-based testbenches, including drivers, monitors, scoreboards, sequences, and reference models for diverse hardware interfaces. Utilize and extend industry-standard verification methodologies such as UVM (Universal Verification Methodology) for scalable and reusable test environments. Plan, track, and manage verification efforts using Agile tools such as Jira while ensuring alignment with program schedules and deliverables. Analyze functional and code coverage metrics to ensure thorough validation of design intent and identify verification gaps. Debug complex hardware and testbench issues by working closely with RTL engineers using languages such as SystemVerilog and VHDL/Verilog. Manage regression testing environments, compute resources, and simulation workflows using tools such as Questa, Cadence Xcelium, and Synopsys VCS. Evaluate and adopt emerging AI-driven verification tools and agentic workflows to improve productivity and coverage efficiency. Collaborate with cross-functional engineering teams to define and refine verification requirements and quality standards. Drive technical issues to resolution with strong ownership from identification through closure. Requirements: 8+ years of experience in design verification for ASIC or FPGA systems. Strong hands-on expertise in UVM-based testbench development and SystemVerilog programming. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline. Deep understanding of digital design fundamentals, timing considerations, and hardware architecture concepts. Experience working with industry-standard simulators such as Questa, Xcelium, or VCS. Familiarity with object-oriented programming principles and reusable testbench desig