SeniorDesignVerificationEngineer

## Accountabilities Lead end-to-end verification of IP and subsystem-level designs, ensuring robust coverage, high-quality execution, and timely delivery of verification milestones. Own verification planning, test development, and coverage closure for assigned IP blocks and features Build and maintain scalable verification environments using UVM, SystemVerilog, and constrained-random methodologies Develop reusable testbenches, checkers, and automation frameworks to improve verification efficiency Collaborate with architecture, design, and software teams for spec reviews, debugging, and issue resolution Drive root-cause analysis of simulation failures and ensure timely defect closure Execute functional coverage planning and contribute to sign-off quality metrics Participate in simulation and formal verification activities to enhance verification depth and confidence Mentor junior engineers and support continuous improvement in verification practices and code quality Requirements You bring strong experience in design verification with a proven track record of delivering high-quality IP and subsystem verification in complex silicon environments. You are highly skilled in debugging, protocol analysis, and building reusable verification infrastructures. 8–12 years of experience in design verification with IP and subsystem-level exposure Strong expertise in interconnect protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe Deep knowledge of UVM, SystemVerilog, SVA, and coverage-driven verification methodologies Hands-on programming experience in SystemVerilog, C/C++, and Python for verification and automation Strong understanding of cache coherency and memory consistency models Experience collaborating across architecture, design, and software teams in complex projects Familiarity with AI-assisted development workflows for coding, debugging, and test generation Experience with formal verification, emulation, or FPGA-based validation is a plus Exposure to system-level IPs