Micron Technology
Semiconductor
SeniorDesignEngineer
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“Senior Design Engineer at Micron Technology. Skills: NAND Flash design, Compute-in-Memory, Circuit design, Python. Develop array waveforms. Develop timing conditions”
Industry & Context.
Circuit debugging; Problem-solving; Troubleshooting
What They're Looking For.
Must Have
MS in electrical engineering, 4+ years NAND design experience, Prior CIM projects led or contributed, Semiconductor and device physics fundamentals, Analog/mixed-signal circuit design fundamentals, Semiconductor reliability issues understanding, Electro-migration (EM) and IR analysis understanding, Circuit debugging skills, Problem-solving skills, Circuit verification experience, Circuit optimization experience, Layout planning experience, Parasitic extraction experience, Guiding layout experience, Python coding skills, Bash/Tcl coding skills, Working with structured data, Version control experience
Nice to Have
Ph.D. preferred, HSPICE knowledge, Fast SPICE knowledge, Verilog knowledge, Cadence design familiarity, LVS tools familiarity, DRC tools familiarity, Scripting language experience, Linux/UNIX familiarity
What You'll Do.
Develop array waveforms
Develop timing conditions
Develop biasing conditions
Collaborate with Firmware team
Collaborate with Analog team
Collaborate with Design validation teams
Plan wordline path architecture
Plan bitline path architecture
Determine circuit block placement
Integrate circuit blocks
Perform die size analysis
Perform cost-benefit analysis
Evaluate NAND power consumptions
Improve NAND power consumptions
Generate Xpath schematics
Generate Ypath schematics
Generate Array schematics
Integrate Core schematics
Run block level simulations
Oversee layout implementation
Run subsystem simulations
Run fullchip simulations
Build Python-based AI utilities
Interface with EDA environments
Accelerate design tasks
Automate environment setup
Automate corner execution
Automate regression runs
Automate documentation
Implement predictive design techniques
Implement predictive layout techniques
Review technical documentation
Generate technical documentation
Support pathfinding efforts
Support prototype efforts
Explore CIM use cases
Define viable compute primitives
Support Product Engineering groups
Support Process Integration groups
Support Assembly groups
Support Marketing groups
Enable manufacturable CIM features
Enable testable CIM features
Evaluate system-level value
Evaluate system-level cost
Evaluate system-level quality
Evaluate system-level reliability
Evaluate time-to-market impacts
How You'll Work.
Team & Collaboration
Collaborate with Firmware team; Collaborate with Analog team; Collaborate with Design validation teams; Collaborate with project teams; Work with system teams; Work with algorithm teams; Work with Product Engineering; Work with Test; Work with Probe; Work with Process Integration; Work with Assembly; Work with Marketing
Communication Scope
Technical documentation
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Sr. or Staff Design Engineer in the NVE Design Engineering Core group at Micron Technology, Inc., you will contribute to the development of memory products that are outstanding, using your specialized knowledge and Micron proprietary methods of designing and analyzing core and mixed circuits used in the development of memory products! **_What’s Encouraged Daily!_** * Develop array waveforms with detailed timing and biasing conditions of array signals for conventional NAND Flash operation as well as Compute‑in‑Memory (CIM) / near‑memory compute modes. This requires in‑depth familiarity with NAND Flash read, program and erase algorithms, and how array‑level biasing, sensing, and accumulation mechanisms can be reused or extended for in‑memory compute (e.g., analog MAC, resistive summation, multi‑level sensing). * Collaborate with Firmware team, Analog team and Design validation teams during actual implementation of waveforms. * Plan the wordline and bitline path architecture according to area, performance and power specifications. Determine the placement of these circuit blocks and collaborate with project teams in integrating these circuit blocks to the chip plan. * Perform die size cost and benefits analysis of new array circuits and algorithms prior to implementation. Working closely with other functional teams to evaluate, analyze, and improve NAND power consumptions. * Generate Xpath, Ypath and Array schematics during project execution and work with project teams integrating the Core schematics into the fullchip schematics. Run block level simulations of the circuits using spice simulator and oversee layout implementation of the circuits. Run subsystem and
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