NVIDIA
AI computing
SeniorASICTimingEngineer
“Senior ASIC Timing Engineer at NVIDIA. Skills: ASIC Timing Analysis, Static Timing Analysis (STA), timing convergence, timing constraints generation and management, ECOs, physical design optimization. Drive Timing Analysis and Closure for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.. Devise timing closure strategies.”
What You'll Achieve.
timing closure; timing and power convergence; success of our innovative projects; advancement of our technology; improve timing convergence flows
Industry & Context.
challenge yourself; tackle hard opportunities
What They're Looking For.
Must Have
BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’ experience in Timing and STA, Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management., Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis., Experience in physical design and optimization e. g. , synthesis, placement, routing, logic restructuring, etc. to improve timing and power., Expertise and in-depth knowledge of industry standard STA and timing convergence tools., Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.
Nice to Have
Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPU or SOCs, Background in logic synthesis and equivalence checking/FV., Understanding of DFT logic and experience with DFT timing closure for various modes e. g. , scan, BIST, etc., Understanding and timing closure of digital logic/macros in AMS designs/IPs., Experience in methodology and/or flow development as well as automation.
What You'll Do.
Drive Timing Analysis and Closure for NVIDIA's GPUs
and SoCs at block level
Devise timing closure strategies.
Create timing constraints.
Drive timing and power convergence.
Improve timing convergence flows.
How You'll Work.
Team & Collaboration
Collaborate with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
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