NVIDIA
AI computing
SeniorASICRTLIntegrationandNetlistingEngineer
“Senior ASIC RTL Integration and Netlisting Engineer at NVIDIA. Skills: ASIC RTL Integration, Netlisting, Physical Design, Logic Synthesis, Equivalence Checking. Drive physical design integration and implementation of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level. Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones”
Industry & Context.
What They're Looking For.
Must Have
BS (or equivalent experience) in Electrical or Computer Engineering with 8+ years’ experience or MS (or equivalent experience) with 5+ years’ experience in RTL integration and netlisting domains, understanding of RTL and RTL hierarchy and associated infrastructures, Hands on experience with logic synthesis and associated verification such as equivalence checking, Background in gate level netlist verification and completeness with respect to power, testability, etc, Expertise and in-depth knowledge of industry standard EDA tools
Nice to Have
Expertise in understanding on clock-domains, async interfaces and MTBF analysis, Solid understanding of Physical Design flows, design constraints, timing and power convergence, Proficiency in programming/scripting languages (Python, TCL etc) and/or AI tools (Cursor, Copilot, etc)
What You'll Do.
Drive physical design integration and implementation of high-frequency and low-power CPUs
and/or full chip level
Drive RTL integration
along with all physical netlist deliverables across various milestones
Drive formal equivalence checking
netlist quality checks
asynchronous checking including clock domain crossing checks and MTBF analysis
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