NVIDIA

Technology

SeniorASICFloorplanDesignEngineer

$196–368k Santa Clara, California, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior ASIC Floorplan Design Engineer at NVIDIA. Skills: ASIC Floorplan Design, VLSI, Physical Design. Develop floorplans during early chip development. Craft floorplans during early chip development”

Industry & Context.

Technology

What They're Looking For.

Must Have

Masters Degree in EE, CS, or CE, 12+ years relevant work experience, Deep hardware engineering background, VLSI concentration, Computer Architecture concentration, Experience in Verilog, Experience in System Verilog, Experience with HVL, Experience with CAD, Experience with physical design methodologies, Experience with chip floorplan, Experience with power/clock distribution, Experience with packaging, Experience with P&R, Experience with timing closure, Python programming language experience, Perl programming language experience, C/C++ programming language experience

Nice to Have

Experience driving large scale ASIC floorplan development

What You'll Do.

Develop floorplans during early chip development

Craft floorplans during early chip development

Optimize floorplans during early chip development

Drive area review process

Collaborate with ASIC design team

Identify area improvement opportunities

Identify interconnect improvement opportunities

Identify floorplan improvement opportunities

Solve routing congestion issues

Influence early design decisions

Influence physical implementation decisions

Build tools to optimize chip area

Build tools to optimize speed of execution

Improve infrastructure to optimize chip area

Improve infrastructure to optimize speed of execution

How You'll Work.

Team & Collaboration

Architects; Design leads; Physical design leads; Package leads; ASIC design team

Full Job Description

We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. **What you will be doing:** * Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. * Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities * Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. * You will build tools and improve existing infrastructure to optimize chip area and speed of execution. **What we need to see:** * Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience * 12+ years of relevant work experience * A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture. * Experience in Verilog, System Verilog or similar HVL * Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure. * Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview. * Python, Perl and C/C++ programming language experience **Ways to stand

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