NVIDIA

Technology

SeniorASICDesignVerificationEngineer

$136–219k Santa Clara, California, United States FULL TIME Remote Friendly
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Senior ASIC Design Verification Engineer at NVIDIA. Skills: ASIC Design Verification, GPU, SoC, Hardware security. Develop innovative IPs for hardware security. Develop innovative IPs for clocking”

What You'll Achieve.

Delivering bug-free first silicon

Industry & Context.

Technology
Problems you'll solve

Debugging; Analytical skills; Root cost analysis

What They're Looking For.

Must Have

5+ years experience in unit level or sub-system level verification, Proficiency in Object Oriented Programming, Proficiency in Verilog, Proficiency in System Verilog, Proficiency in UVM, Proficiency in SVA, Proficiency in functional coverage development, Proficiency with VCS or equivalent simulation tools, Debugging skills required, Analytical skills required

Nice to Have

MS preferred in Electrical, Computer Engineering, 3+ years experience in unit level or sub-system level verification, Proficiency in developing and implementing agentic AI workflows, Knowledge or work experience in custom designed IPs solutions, Good understanding of behavioral real number modeling, Knowledge or work experience in co-simulation environments, Knowledge or work experience in Gate Level Simulation, Knowledge or work experience in Formal Equivalence domains, Proficiency in scripting language, Proficiency in Perl, Proficiency in Tcl, Proficiency in Make files, Proficiency in automation methods/algorithms

What You'll Do.

Develop innovative IPs for hardware security

Develop innovative IPs for clocking

Develop innovative IPs for voltage regulation

Develop innovative IPs for silicon correlation

Own unit level verification of IPs

Own sub-system level verification of IPs

Create functional test plans

Verify using advanced verification tools

Build verification infrastructure

Reform verification infrastructure

Build verification methodologies

Reform verification methodologies

Engage in design specification development

Participate in architecture discussions

Participate in intent discussions

Participate in implementation discussions

Enable system level integration

Work with partner teams for test development

Work with partner teams for debug

Deliver Verification IPs

Play key role in development of agentic AI

Play key role in deployment of agentic AI

How You'll Work.

Team & Collaboration

Partner teams; On-site teams; Remote teams

Full Job Description

NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence performance of the next generation GPU and SoC, allowing you to have real impact in a multifaceted, technology-focused company with product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! We have crafted a team of highly motivated people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. **What you will be doing:** * Work as part of Circuit Solutions Group to develop various innovative IPs for hardware security, clocking, voltage regulation and silicon correlation. * Own the unit and sub-system level verification of various IPs, create functional test plans, and verify using advanced verification tools, flows and methodologies. * Build and reform world class verification infrastructure and methodologies to meet the unique demands of custom designed IPs. * Engage in design specification development by participating in discussions on architecture, intent, and implementation of the various IPs. * Enable system level integration by working with partner teams for test development & debug and delivering Verification IPs. * Play a key role in development and deployment of agentic AI frameworks for DV workflows such as stimulus generation, regression triage, debug, root cost analysis etc... **What we need to see:** * BSEE (or equivalent experience) with 5+ years' experience in unit level or sub-system level verification or MS preferred in Electrical, Computer Engineering with 3+ years’ experience in unit level or sub-system level verification. * Proficiency in Object Oriented Programming, Verilog, System Verilog, UVM, SVA and functional coverage development. * Strong skills with VCS or equivalent simulation tools like

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