Blue Origin

Spaceflight

SeniorASICDesignVerificationEngineer

$198–277k Exton, Pennsylvania, United States FULL TIME Remote Friendly
The Brief

“Senior ASIC Design Verification Engineer at Blue Origin. Skills: ASIC Design Verification, System Verilog, UVM, verification planning, coverage closure. Lead verification planning and execution for complex blocks or subsystems. Develop sophisticated UVM environments, reference models, scoreboards, protocol monitors, and assertions”

What You'll Achieve.

ensure robust, high-quality silicon; measurable coverage goals; functional coverage closure; regression health; verification signoff readiness

Industry & Context.

Spaceflight
Problems you'll solve

problem solvers

Eligibility Requirements

U. S. citizen or national, U. S. permanent resident (i. e. current Green Card holder), or lawfully admitted into the U. S. as a refugee or granted asylum, Blue’s Standard Background Check, Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation, Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10, 001 lbs. and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training, Ability to obtain and maintain Merchant Mariner Credential, which includes pre-employment and random drug testing as well as DOT physical

What They're Looking For.

Must Have

BS or MS in Electrical Engineering, Computer Engineering, or related field, 5–8+ years of ASIC/SoC verification experience, Deep hands-on expertise in System Verilog and UVM, understanding of verification planning, assertions, and coverage closure, Experience verifying complex digital control and datapath logic, Proven debugging capability across RTL, testbench, and system interactions, Ability to work effectively across multidisciplinary engineering teams

Nice to Have

Background in Space based communications, wireless communications, or modemaseband hardware, Experience verifying LDPCCH/FEC blocks, framing engines, beamforming logic, or DSP pipelines, Familiarity with formal verification tools and methodologies, Experience with low-power verification, CDC/RDC verification, or reset-domain behavior, Knowledge of high-speed interface verification and hardware/software interactions

What You'll Do.

Lead verification planning and execution for complex blocks or subsystems

Develop sophisticated UVM environments

Translate architecture and design specifications into comprehensive verification strategies and measurable coverage goals

Drive functional coverage closure

and verification signoff readiness

Identify verification gaps

and high-risk scenarios early in the development cycle

Review testbench architecture

and debug methodologies for technical excellence

and post-silicon debug activities as needed

How You'll Work.

Team & Collaboration

Collaborate closely with design, systems, DFT, firmware, and physical design teams; Ability to work effectively across multidisciplinary engineering teams

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