Annapurna Labs
Technology
SeniorASICDesignInfrastructure&Methodologiesengineer,MLAMI
“Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI at Annapurna Labs. Skills: ASIC Design, Infrastructure, Methodologies, Automation. Develop methodologies. Implement methodologies”
Industry & Context.
Root cause analysis
What They're Looking For.
Must Have
7+ years ASIC implementation, 7+ years synthesis, 7+ years STA, 7+ years physical design, deep sub-micron nodes (16nm or smaller) experience, 7+ years digital design, 7+ years communication systems, 7+ years full-custom analog layout, 7+ years RF layout, 7+ years wireless communications systems, 7+ years wireless implementation, 8+ years automation frameworks, 8+ years Post-Silicon Flow, 7+ years verification, 5+ years UVM, 5+ years C, 5+ years System C, 5+ years scripting
Nice to Have
Master's degree or Ph.D., RTL coding and debug experience, performance, power, area analysis experience, trade-offs experience, modern ASIC/FPGA design tools experience, modern ASIC/FPGA verification tools experience, SOC bring-up experience, post-silicon validation experience
What You'll Do.
Develop methodologies
Implement methodologies
Maintain high-quality standards
Collaborate with vendors
Evaluate design tools
Evaluate tool versions
Qualify tool versions
How You'll Work.
Team & Collaboration
Architects; Designers; Verification engineers; Cross-functional team members
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