NVIDIA
SeniorASICDesignEngineerXBARIP
“Senior ASIC Design Engineer - XBAR IP at NVIDIA. Skills: ASIC Design, RTL Design, Verilog. Own micro-architecture. RTL development”
What You'll Achieve.
deliver a fully verified, synthesis/timing clean design; ensure design meets timing; ensure design meets interface requirements; ensure design is routable; ensure that S/W is tested
Industry & Context.
Good debugging and problem solving skills
What They're Looking For.
Must Have
BS / MS or equivalent experience, 5+ years of design experience, Experience in RTL design of complex design units for at least two or three projects, Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug, Expertise in Verilog
Nice to Have
Design experience in memory subsystem or network interconnect IP, Good debugging and problem solving skills, Scripting knowledge (Python/Perl/shell), Leadership experience in leading small 2-3 member teams, Good interpersonal skills and ability & desire to work as a part of a team
What You'll Do.
Own micro-architecture
Micro-architect features
Collaborate with verification teams
Co-operate with timing teams
Interact with FPGA teams
Work on post-silicon verification
How You'll Work.
Team & Collaboration
Work with architects; Collaborate with verification teams; Co-operate with timing teams; Interact with FPGA teams; Work with S/W teams; work as a part of a team
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