Elevate Semiconductor
semiconductor technology
SeniorAnalogICLayoutEngineer
“Senior Analog IC Layout Engineer at Elevate Semiconductor. Skills: physical layout of analog and mixed-signal integrated circuits, floorplanning and placement, LVS and DRC verification. Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level. Conducting floorplanning and placement of circuit components to optimize area, performance, and power”
What You'll Achieve.
optimize area, performance, and power; ensure compliance with process design rules; ensure layout accuracy; optimize overall chip performance; deliver innovative and cost-effective solutions
Industry & Context.
Troubleshooting and resolving issues related to layout verification and manufacturing
Must be able to work onsite in San Diego, CA.
What They're Looking For.
Must Have
Bachelor’s degree in Electrical Engineering or a related field, Minimum of 5 years of professional experience in analog and mixed-signal IC layout design, knowledge of analog CMOS circuits and device physics fundamentals, Solid understanding of the IC design, qualification, and manufacturing lifecycle, Hands-on experience with industry-standard EDA tools for analog and mixed-signal design (e. g. , Cadence, Mentor Graphics, Tanner), Proficiency in performing LVS and DRC verification using Cadence or Mentor tools
Nice to Have
Layout experience with STI High voltage (100V+) BCD and LDMOS processes, Layout experience with mixed voltage (multiple supply rails, 6 or more) domains, Layout experience with high speed multi Gbps circuits., Layout experience in ultra-high accuracy and precision circuits., Layout experience with high resolution data converters., Layout experience with BiCMOS process technology., Programming and scripting ability a plus, particularly in SKILL and Calibre scripts
What You'll Do.
Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level
Conducting floorplanning and placement of circuit components to optimize area
Verifying layouts using industry-standard tools for LVS (Layout vs. Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
Troubleshooting and resolving issues related to layout verification and manufacturing
How You'll Work.
Team & Collaboration
Collaborate with a cross-functional team to optimize silicon design; Collaborating closely with design engineers to understand circuit specifications and ensure layout accuracy; Working with cross-functional teams, including digital design and packaging, to optimize overall chip performance
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