Renesas Electronics
Semiconductor
SeniorAnalogEngineeringManager
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“Senior Analog Engineering Manager at Renesas Electronics. Skills: DDR5 PHYs, DDR6 architectures, Analog/mixed-signal design, People leadership. Own and guide architecture of DDR5 PHYs. Guide design of DDR5 PHYs”
Industry & Context.
Timing closure; Jitter analysis; Noise analysis; SI/PI analysis; PVT robustness; Silicon debug; Yield improvement; Architectural trade-offs
What They're Looking For.
Must Have
Bachelor’s or Master’s degree in Electrical Engineering, 12+ years analog/mixed-signal IC design, 5+ years people-management experience, 5+ years technical leadership experience, Proven hands-on delivery of DDR5 PHYs, Proven hands-on delivery of late-stage DDR4 designs
Nice to Have
PhD preferred, Direct involvement in DDR6 architectural studies, Direct involvement in early-stage DDR6 development, Experience at advanced nodes (7nm, 5nm, and below), Background in multi-generation memory PHYs, Background in scalable PHY platforms, Ability to lead teams delivering multiple concurrent tape-outs
What You'll Do.
Own and guide architecture of DDR5 PHYs
Guide design of DDR5 PHYs
Guide implementation of DDR5 PHYs
Contribute to DDR6-ready architectures
Provide technical oversight for analog blocks
Provide technical oversight for mixed-signal blocks
Design high-speed TX/RX datapaths
Design advanced equalization circuits
Design termination circuits
Design training circuits
Design DLL/PLL-based clocking solutions
Design multi-GHz clocking solutions
Design voltage generation circuits
Design reference generation circuits
Design power-aware IO
Drive closure on timing
Drive closure on jitter
Drive closure on noise
Drive closure on SI/PI
Drive closure on PVT robustness
Ensure compliance with JEDEC DDR5 specifications
Align with evolving DDR6 standards
Lead post-silicon bring-up
Lead silicon characterization
Lead yield improvement
Build a team of designers
Lead a team of designers
Mentor a team of designers
Set technical direction
Set performance expectations
Set development plans
Foster a culture of technical rigor
Foster a culture of ownership
Foster a culture of execution excellence
Own DDR5/DDR6 PHY execution
Partner closely with Digital PHY teams
Partner closely with controller teams
Partner closely with SoC integration teams
Partner closely with system architecture teams
Partner closely with Package teams
Partner closely with PCB teams
Partner closely with SI/PI teams
Partner closely with validation teams
Partner closely with Product teams
Partner closely with program management teams
Partner closely with customers
Interface with foundries
Interface with IP vendors
Interface with standards bodies
Establish design methodologies
Establish signoff methodologies
Drive continuous improvement in simulation accuracy
Drive continuous improvement in mixed-signal verification
Drive continuous improvement in silicon debug efficiency
Lead long-term DDR5 sustainment planning
Lead DDR6 technology roadmap planning
Plan architectural trade-offs
Plan scaling strategies
Anticipate challenges from data-rate scaling
Anticipate challenges from power efficiency
Anticipate challenges from advanced process technologies
How You'll Work.
Team & Collaboration
Partner closely with Digital PHY; Partner closely with controller teams; Partner closely with SoC integration; Partner closely with system architecture; Partner closely with Package teams; Partner closely with PCB teams; Partner closely with SI/PI teams; Partner closely with validation teams; Partner closely with Product; Partner closely with program management; Partner closely with customers; Interface with foundries; Interface with IP vendors; Interface with standards bodies
Communication Scope
Technical communication; Executive communication
Process & Methodology
Program ownership, Schedule balancing, Quality balancing, Risk balancing, Roadmap planning
Full Job Description
We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. This role requires deep technical expertise in high-speed memory interfaces, combined with strong people leadership and program ownership. The successful candidate will manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR6-class signaling and architecture Technical Leadership (DDR5 / DDR6) * Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures. * Provide technical oversight for critical analog and mixed-signal blocks, including: * High-speed TX/RX datapaths * Advanced equalization, termination, and training circuits * DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates. * Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction. * Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation. People & Organization Leadership * Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces. * Set technical direction, performance expectations, and development plans for senior and principal engineers. * Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs. * Foster a culture of technical rigor, ownership, and execution excellence. Program & Cross-Functional Execution * Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk * Partner closely with: Digital PHY and controller teams SoC integration and system architecture, Package, PCB, SI/PI, and validation teams, Product, progr
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