Renesas Electronics
Tech / AI / Software
SeniorAnalogEngineeringManager
Neural analysis suggests this role is
optimal for mid candidates.
“Senior Analog Engineering Manager at Renesas Electronics. Skills: DDR5 PHY development, DDR6 architecture, Analog/Mixed-signal IC design, High-speed memory interfaces, People Management. Lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. Manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs”
What You'll Achieve.
end-to-end delivery of high-performance, low-power DDR PHYs; silicon bring-up; characterization; debug; yield improvement; customer-system correlation; successful delivery and future readiness; maximize your performance and wellbeing
Industry & Context.
Drive closure on timing, jitter, noise, SI/PI, and PVT robustness; Anticipate challenges from data-rate scaling, power efficiency, and advanced process technologies
What They're Looking For.
Must Have
Bachelor’s or Master’s degree in Electrical Engineering, 12+ years of experience in analog/mixed-signal IC design with deep focus on high-speed memory interfaces, 5+ years of people-management and technical leadership experience, Proven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5, expertise in: High-speed IO design and signal integrity, PLL/DLL and low-jitter clocking architectures, Mixed-signal verification and silicon validation, Advanced CMOS process considerations for IOs
Nice to Have
PhD preferred, Direct involvement in DDR6 architectural studies or early-stage development, Experience at advanced nodes (7nm, 5nm, and below), Background in multi-generation memory PHYs or scalable PHY platforms, Ability to lead teams delivering multiple concurrent tape-outs, written and verbal communication skills across technical and executive audiences
What You'll Do.
Lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs
Manage a team responsible for end-to-end delivery of high-performance
Own and guide the architecture
and implementation of DDR5 PHYs and contribute to DDR6-ready architectures
Provide technical oversight for critical analog and mixed-signal blocks
Drive closure on timing
and PVT robustness for aggressive DDR5/DDR6 data rates
Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards
Lead post-silicon bring-up
and yield improvement
and mentor a team of analog and mixed-signal designers
Set technical direction
performance expectations
and development plans for senior and principal engineers
Own DDR5/DDR6 PHY execution balancing schedule
Establish robust design and signoff methodologies for next-generation high-speed PHYs
Drive continuous improvement in simulation accuracy
mixed-signal verification
and silicon debug efficiency
Lead long-term DDR5 sustainment and DDR6 technology roadmap planning
How You'll Work.
Team & Collaboration
Partner closely with: Digital PHY and controller teams; SoC integration and system architecture teams; Package teams; PCB teams; SI/PI teams; validation teams; Product teams; program management teams; customers; Interface with foundries, IP vendors, and standards bodies
Communication Scope
written and verbal communication skills across technical and executive audiences
Process & Methodology
program ownership, Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk, disciplined risk management
Full Job Description
We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. This role requires deep technical expertise in high-speed memory interfaces, combined with strong people leadership and program ownership. The successful candidate will manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR6-class signaling and architecture Technical Leadership (DDR5 / DDR6) * Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures. * Provide technical oversight for critical analog and mixed-signal blocks, including: * High-speed TX/RX datapaths * Advanced equalization, termination, and training circuits * DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates. * Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction. * Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation. People & Organization Leadership * Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces. * Set technical direction, performance expectations, and development plans for senior and principal engineers. * Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs. * Foster a culture of technical rigor, ownership, and execution excellence. Program & Cross-Functional Execution * Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk * Partner closely with: Digital PHY and controller teams SoC integration and system architecture, Package, PCB, SI/PI, and validation teams, Product, progr
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