Etched
AI inference system
RTLInternSummer2027
“RTL Intern - Summer 2027 at Etched. Skills: Microarchitecture design, Logic implementation in Verilog, RTL block development, ASIC/SoC design concepts, Verification, Physical design. Design microarchitecture. Implement logic in Verilog”
Industry & Context.
12-week paid internship, Generous housing support for those relocating, Daily lunch and dinner in our office, Based at our office in San Jose, CA, Direct mentorship from industry leaders and world-class engineers
What They're Looking For.
Must Have
Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field, Familiarity with high-speed digital logic, Exposure to ASIC or SoC design concepts, Familiarity with SystemVerilog, UVM, or Python, Familiarity with verification work and writing test benches, Familiarity with physical design flows and tooling, Able to learn quickly about transformers and other aspects of modern artificial intelligence
Nice to Have
Familiarity with transformer models and machine learning, Familiarity with numerical representations and functions, Familiarity with clocking and reset schemes, Ability to program with Python or another scripting language
What You'll Do.
Design microarchitecture
Implement logic in Verilog
Work with cutting-edge machine learning architectures
Contribute to RTL block development
Participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback
Applying for this RTL Intern - Summer 2027 role?
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