Micron Technology

Technology

ProductYieldEnhancement(PYE)Engineer

$1300–1950k ~AI est. Taichung, Taiwan FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Mid+ candidates.

The Brief

“Product Yield Enhancement (PYE) Engineer at Micron Technology. Skills: Failure Analysis, Electrical Characterization, Physical Characterization, Data Analysis. Perform Electrical Failure Analysis. Perform Fault Isolation”

What You'll Achieve.

Enhanced product reliability; Rapid production ramp; Early time to market

Industry & Context.

Technology
Problems you'll solve

Problem-solving skills; Analytical skills

What They're Looking For.

Must Have

Bachelor’s Degree in Electrical or Electronics Engineering, Electro-Optical Engineering, Photonics, Microelectronics, and Semiconductor Technology, Extensive understanding of physical and logical semi-conductor design, Understand various PFA and de-processing techniques, In depth understanding of CMOS process fabrication levels, Knowledge of package assembly flow, Understand reliability concerns, Expertise with process and assembly related defects, Understand probe, backend test and qualification flows, Computer aided layout and schematic experience, Semiconductor process coursework and/or experience, UNIX and Programming experience, Experience working in teams, Ability to work well with others

Nice to Have

Course work in VLSI design, Course work in semiconductor device physics

What You'll Do.

Perform Electrical Failure Analysis

Perform Fault Isolation

Operate uMate bench test platform

Operate Hamamatsu iPHEMOS

Operate Thermo Fisher ELITE

Operate photon stimulating emission tools

Operate thermal stimulating emission tools

Operate laser stimulating emission tools

Characterize backend test fail signatures

Model backend test fail signatures

Characterize internal qualification fail signatures

Model internal qualification fail signatures

Characterize RMA fail signatures

Model RMA fail signatures

Use layout/schematic for fault isolation

Use layout/schematic for fail signature modeling

Understand Fabrication Process

Understand Package Assembly

Provide Clear Fail Signature Information

Provide Comprehensive Fail Signature Information

Generate failure analysis reports

Perform fab data extractions

Perform probe data extractions

Perform backend data extractions

How You'll Work.

Team & Collaboration

Communicate failure analysis findings; Coordinate failure analysis findings

Communication Scope

Good communication skills

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Yield Enhancement (PYE) Engineer for Micron Technology, Inc., you will work with a team responsible for taking next generation devices from design to mass production. You will focus on failure analysis of test, internal qualification, and RMA failures, allowing for enhanced product reliability, rapid production ramp and early time to market. Your primary areas of responsibility will utilize fault isolation with a combination of electrical and physical characterization techniques combined with data analysis to identify physical defects introduced by process level or assembly step. Additionally, you will be responsible for communicating and coordinating failure analysis findings with Management, Product, Process, Assembly and Quality Assurance groups. **The general responsibilities of the position are the following:** * _Perform Electrical Failure Analysis and Fault Isolation_ * ​Operate uMate bench test platform * _**Operate Hamamatsu iPHEMOS, Thermo Fisher ELITE and other photon, thermal, or laser stimulating emission tools**_ * Characterize or model backend test, internal qualification, and RMA fail signatures * Extensive understanding of physical and logical semi-conductor design * Use layout/schematic to aid in fault isolation and fail signature modeling * Understand various PFA and de-processing techniques for failures * _Understanding Fabrication Process and Package Assembly_ * In depth understanding of CMOS process fabrication levels, steps, and methodologies * Knowledge of the steps and details involved in the package assembly flow * Understand reliability concerns that can cause delayed breakdown fail signatures * Extensive expertise with pro

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