NVIDIA
Semiconductor
ProductDevelopmentLabEngineer
Neural analysis suggests this role is
optimal for Mid candidates.
“Product Development Lab Engineer at NVIDIA. Skills: ATE lab operations, post-silicon validation, Failure Analysis (FA) workflows, Semiconductor Lab management, ATE testing operations, Product Engineering support. Lead daily operations and resource management at external ATE labs (e. g. , SPIL) to ensure engineering test continuity and maximize tester utilization during critical NPI phases. Perform comprehensive reject verification (L1/L2) and PFA isolation for Data Center GPU (GB100/GB110) and S”
What You'll Achieve.
accelerate our post-silicon validation processes; ensure the smooth execution of Failure Analysis (FA) workflows; maximize tester utilization during critical NPI phases; accelerate yield learning and DPPM tracking
Industry & Context.
PFA isolation; Failure Analysis (FA) workflows
strict adherence to ESD safety protocols
What They're Looking For.
Must Have
Bachelor’s degree in Electrical Engineering, Electronic Engineering, Computer Science, or a related field, or equivalent experience, 3+ years of experience in Semiconductor Lab management, ATE testing operations, or Product Engineering support, Proven expertise in coordinating with external OSATs or ATE labs, with a deep understanding of SPIL or similar foundry operational environments, foundational knowledge of ATE analysis, Failure Analysis (EFA/PFA) workflows, and the ability to interpret complex test logs or Shmoo plots, Proficiency in communication for cross-functional collaboration and the ability to manage dynamic hardware logistics in a fast-paced NPI environment
Nice to Have
Experience with SMT7 or SMT8 test environments is a plus, Familiarity with NVIDIA’s internal tools or scripting (Linux/Unix shell) for log parsing, Background in handling high-power Data Center products (e.g. , GB100/GB110) or Automotive SoCs
What You'll Do.
Lead daily operations and resource management at external ATE labs (e.
, SPIL) to ensure engineering test continuity and maximize tester utilization during critical NPI phases, Perform comprehensive reject verification (L1/L2) and PFA isolation for Data Center GPU (GB100/GB110) and SoC (T264) projects to accelerate yield learning and DPPM tracking, Manage end-to-end logistics for FA chip shipments, including Work Order (traveller) control, remote request execution, part delivery, and strict adherence to ESD safety protocols, Optimize technical operations by utilizing and verifying FA automation tools (e.
, EDF to Log extractors, Bitmap SEFA flows) across SMT7 and SMT8 platforms.
How You'll Work.
Team & Collaboration
Partner with internal PDE/PTE teams and external foundry engineering teams through weekly technical sync-ups to align on failure analysis status and test program downloads
Communication Scope
Proficiency in communication for cross-functional collaboration; weekly technical sync-ups
Process & Methodology
resource management, logistics management, Work Order (traveller) control
Full Job Description
NVIDIA is looking for a hands-on Lab Engineer to lead our ATE lab operations and accelerate our post-silicon validation processes. As the complexity of our Data Center (GPU) and SoC products increases , we need a dedicated professional to excute and support our external lab resources (SPIL), optimize tester utilization, and ensure the smooth execution of Failure Analysis (FA) workflows. You will play a pivotal role in bridging the gap between our internal engineering teams and external foundry partners. **What you 'll be doing:** * Lead daily operations and resource management at external ATE labs (e.g., SPIL) to ensure engineering test continuity and maximize tester utilization during critical NPI phases. * Perform comprehensive reject verification (L1/L2) and PFA isolation for Data Center GPU (GB100/GB110) and SoC (T264) projects to accelerate yield learning and DPPM tracking. * Manage end-to-end logistics for FA chip shipments, including Work Order (traveller) control, remote request execution, part delivery, and strict adherence to ESD safety protocols. * Partner with internal PDE/PTE teams and external foundry engineering teams through weekly technical sync-ups to align on failure analysis status and test program downloads. * Optimize technical operations by utilizing and verifying FA automation tools (e.g., EDF to Log extractors, Bitmap SEFA flows) across SMT7 and SMT8 platforms. **What we need to see:** * Bachelor’s degree in Electrical Engineering, Electronic Engineering, Computer Science, or a related field, or equivalent experience. * 3+ years of experience in Semiconductor Lab management, ATE testing operations, or Product Engineering support. * Proven expertise in coordinating with external OSATs or ATE labs, with a deep understanding of SPIL or similar foundry operational environments. * Strong foundational knowledge of ATE analysis, Failure Analysis (EFA/PFA) workflows, and the ability to interpret complex test logs or Shmoo plots. * Proficiency in com
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