PrincipalValidationLeadEngineer

Your Team, Your Impact The Principal Validation Engineer (Lead) will own the lab validation strategy and execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. This role combines hands-on silicon bring-up and debug with technical leadership of validation activities, including test planning, methodology, and coordination across design, DFT, firmware, and product/test engineering. What You Can Expect Define overall validation strategy and test plans for ASIC/SoC devices with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces, covering functionality, performance, power, margining, and interoperability. Lead silicon bring-up and lab validation, including platform bring-up (boards, power, clocks, resets) and interface‑level validation for CXL/PCIe/DDR/HBM/SerDes. Provide technical direction to other validation engineers, including test plan reviews, debug guidance, and prioritization of tasks and issues. Configure and operate advanced lab equipment: high‑bandwidth oscilloscopes and probes, logic analyzers, PCIe/CXL protocol analyzers, BERTs, pattern generators, power supplies, electronic loads, and environmental chambers. Drive development of lab automation and data analysis infrastructure (Python, TCL, shell, MATLAB or similar) to improve coverage, throughput, and reproducibility. Analyze large data sets to characterize high-speed links and memory interfaces (BER, eye diagrams, jitter, margins, throughput, latency, power) and translate findings into design and validation recommendations. Lead root-cause investigations across silicon, firmware, board design, and test setup; coordinate cross-functional issue closure with design, DFT, firmware, and product/test engineering. Own documentation of validation methodologies, lab setups, and results; communicate status, risks, and mitigation plans to project leadership. Mentor and coach junior validation engineers, helping build a strong, scalable lab validation team and best