NVIDIA

Semiconductor

PrincipalSolutionsArchitectSemiconductorTest

$216–345k Santa Clara, California, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Principal candidates.

The Brief

“Principal Solutions Architect – Semiconductor Test at NVIDIA. Skills: Semiconductor test, ATE platforms, DFT architecture, AI/ML yield learning. Define test development strategy. Lead architectural trade-off decisions”

What You'll Achieve.

Improve yield; Embed data-driven intelligence; Ensure test strategy scales

Industry & Context.

Semiconductor
Problems you'll solve

Architectural trade-off decisions; Yield learning; Outlier detection; Predictive binning; Test time optimization; Root cause analysis

What They're Looking For.

Must Have

15+ years semiconductor test engineering experience, Extensive knowledge in ATE platform architecture, Extensive knowledge in test program development, Extensive knowledge in DFT methodology, Extensive knowledge in yield analysis, Extensive knowledge in test data/ML analytics, Skilled in Advantest V93000, Skilled in Teradyne UltraFLEX/ETS, DFT architectures experience, Scan compression experience, MBIST experience, LBIST experience, JTAG experience, MSEE, MSCE, MSCS or equivalent experience

Nice to Have

Experience with mixed-signal test, Experience with RF test, Experience with high-speed I/O test, ML/AI applied to yield analysis, ML/AI applied to PAT/GDBN outlier screening, ML/AI applied to adaptive test, Knowledge of test data formats, Knowledge of analytics tools, Exposure to advanced packaging test challenges, Prior SEMI standards committees engagement, Prior ATE vendor co-development programs engagement, Ph.D or equivalent experience

What You'll Do.

Define test development strategy

Lead architectural trade-off decisions

Establish architectural guidelines

Serve as liaison for DFT architecture

Influence SoC and IP build reviews

Drive adoption of AI/ML techniques

Define and maintain test roadmaps

Mentor senior and principal test engineers

Engage with ATE vendors

Engage with test IP providers

Engage with industry consortia

How You'll Work.

Team & Collaboration

Manufacturing and product engineering teams; Development teams; Process engineering teams; Product engineering teams; Manufacturing teams; Build and test engineering; Multi-functional teams

Communication Scope

Technical standards; Technical guidelines

Process & Methodology

Roadmaps

Full Job Description

We are seeking a Staff/Principal Solutions Architect to define and lead the technical strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead the architectural vision for device testing from wafer probe to final package test. Your directive includes modernising test infrastructure, improving yield, and embedding data-driven intelligence throughout the test lifecycle. You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios. **What You 'll be doing:** * Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families. * Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow. * Establish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.). * Serve as the senior liaison between build and test engineering for DFT architecture decisions — scan, BIST, JTAG, boundary scan, and embedded compression. * Influence SoC and IP build reviews to ensure testability, observability, and debug-ability * Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization. * Define and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets. * Mentor senior and principal test engineers; cultivate technical standards and guidelines across the test organisation. * Engage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE) on emerging standards and technology directions. **What we need to see:** * 15+ years of hands-on semiconductor test

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