Micron Technology

Semiconductor

PrincipalSoCDesignEngineer,HBM

$250–400k ~AI est. Richardson, Texas, United States FULL TIME Remote Friendly
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Principal SoC Design Engineer, HBM at Micron Technology. Skills: SoC Design, HBM, RTL Development, IP Integration. Design and implement RTL. Integrate internal and third-party IP”

Industry & Context.

Semiconductor
Problems you'll solve

Analytical skills; Problem-solving skills; Root-cause analysis

What They're Looking For.

Must Have

Digital SoC design experience, RTL development experience, SystemVerilog/Verilog proficiency, SoC integration methodologies familiarity, RTL-to-GDS flow experience, Synthesis experience, Static timing analysis experience, Design sign-off considerations experience, Design verification concepts knowledge, Debug workflows knowledge, Complex IP blocks integration experience, EDA tools familiarity, Programming or scripting experience, Analytical skills, Problem-solving skills, Attention to detail

Nice to Have

HBM, DRAM, or memory-centric SoC designs experience, High-speed interfaces familiarity, Clocking strategies familiarity, Reset architectures familiarity, Power management concepts familiarity, DFT concepts exposure, Hardware emulation or acceleration platforms experience, Bachelor’s or Master’s degree, 10 years of experience, Mentor and develop junior engineers ability

What You'll Do.

Design and implement RTL

Integrate internal and third-party IP

Collaborate with SoC architects

Translate specifications into RTL

Participate in SoC-level integration

Support design verification

Resolve functional issues

Resolve performance issues

Resolve connectivity issues

Work closely with physical design

Address synthesis considerations

Address timing considerations

Address power considerations

Address floorplanning considerations

Assist with pre-silicon validation

Assist with post-silicon bring-up

Analyze root-cause of silicon issues

Contribute to design documentation

Contribute to block specifications

Contribute to design reviews

Collaborate cross-functionally

Ensure robust designs

Ensure manufacturable designs

Continuously improve design quality

Continuously improve reusability

Continuously improve development efficiency

How You'll Work.

Team & Collaboration

Cross-functional teams; Global engineering teams

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As an **SoC Design Engineer** , you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet aggressive power, performance, area, and schedule targets. This is a hands‑on technical role focused on RTL design, IP integration, debug, and pre‑/post‑silicon support. **Key Responsibilities** * ### **Key Responsibilities** * Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. * Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). * Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. * Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. * Support design verification through debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues. * Work closely with physical design teams to

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