Sandisk

Technology

PrincipalEngineer,VLSIDesignEngineering

₹45–70L ~AI est. Bengaluru, Karnataka, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for mid candidates.

The Brief

“Principal Engineer, VLSI Design Engineering at Sandisk. Skills: VLSI Design, Verification, UVM, SystemVerilog. Lead verification efforts. Drive functional verification closure”

What You'll Achieve.

Ensure design quality; Ensure silicon success

Industry & Context.

Technology
Problems you'll solve

Root-cause analysis; Debugging

What They're Looking For.

Must Have

7 to 11 years experience, Bachelor's degree, Advanced proficiency C, Advanced proficiency Verilog, Advanced proficiency SystemVerilog, Advanced proficiency UVM, Hands-on experience Xcellium, Hands-on experience Verdi, Hands-on experience JasperGold, Expertise verification lifecycle, Lead technical projects, Manage stakeholder relationships

Nice to Have

Master's degree preferred, Experience NAND flash protocols, Experience memory design verification, Track record mentoring junior engineers, Contribute to process improvements, Experience formal verification methodologies, Experience assertion-based verification

What You'll Do.

Lead verification efforts

Drive functional verification closure

Mentor engineering teams

Collaborate across disciplines

Ensure design quality

Ensure silicon success

Develop verification strategies

Develop verification infrastructure

Design verification environments

Implement verification environments

Develop reusable components

Develop scalable components

Develop bus functional models

Drive functional coverage closure

Ensure comprehensive design validation

Plan functional coverage

Develop functional coverage

Debug functional coverage

Close functional coverage

Collaborate with architects

Collaborate with designers

Collaborate with post-silicon teams

Ensure verification integration

Create verification automation tools

Optimize verification automation tools

Investigate design failures

Debug design failures

Perform root-cause analysis

Contribute to continuous improvement

How You'll Work.

Team & Collaboration

Cross-functional teams; Design architects; RTL designers; Post-silicon validation teams

Communication Scope

Written communication; Verbal communication

Process & Methodology

Technical projects

Full Job Description

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. We are seeking an experienced Principal Engineer, VLSI Design Engineering to lead verification efforts for complex IP blocks and fullchip designs. In this role, you will drive functional verification closure, mentor engineering teams, and collaborate across multiple disciplines to ensure design quality and silicon success. Key Responsibilities: * Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs * Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks * Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards * Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Cov

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