Sandisk
Technology
PrincipalEngineer,VLSIDesignEngineering
Neural analysis suggests this role is
optimal for mid candidates.
“Principal Engineer, VLSI Design Engineering at Sandisk. Skills: VLSI Design, Verification, UVM, SystemVerilog. Lead verification efforts. Drive functional verification closure”
What You'll Achieve.
Ensure silicon success
Industry & Context.
Root-cause analysis; Debug
What They're Looking For.
Must Have
7 to 11 years of relevant experience in VLSI design verification, Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical, Advanced proficiency in C, Verilog, SystemVerilog, and UVM, Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold, Demonstrated expertise across the complete verification lifecycle, Proven ability to lead technical projects and manage stakeholder relationships effectively, Bring in AI/ML/Automation based initiatives, Excellent written and verbal communication skills
Nice to Have
Master's degree preferred, Experience with NAND flash memory protocols, Experience with memory design verification, Track record of mentoring junior engineers, Contributing to process improvements, Experience with formal verification methodologies, Experience with assertion-based verification
What You'll Do.
Lead verification efforts
Drive functional verification closure
Mentor engineering teams
Ensure design quality
Ensure silicon success
Lead development of test plans
Lead execution of test plans
Lead development of verification strategies
Lead development of verification infrastructure
Design verification environments
Implement verification environments
Develop reusable verification components
Develop scalable verification components
Drive functional coverage-driven verification closure
Ensure comprehensive design validation
Develop System Verilog Assertions
Maintain System Verilog Assertions
Collaborate with design architects
Collaborate with RTL designers
Collaborate with post-silicon validation teams
Create verification automation tools
Optimize verification automation tools
Investigate design failures
Debug design failures
Perform root-cause analysis of design failures
Mentor junior engineers
Contribute to continuous improvement
How You'll Work.
Team & Collaboration
Cross-functional teams; Design architects; RTL designers; Post-silicon validation teams
Communication Scope
Written communication; Verbal communication
Process & Methodology
Lead technical projects
Full Job Description
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. We are seeking an experienced Principal Engineer, VLSI Design Engineering to lead verification efforts for complex IP blocks and fullchip designs. In this role, you will drive functional verification closure, mentor engineering teams, and collaborate across multiple disciplines to ensure design quality and silicon success. Key Responsibilities: * Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs * Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks * Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards * Drive functional coverage-driven verification closure and ensure comprehensive design validation including Functional Cov
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