Sandisk
Computer Hardware
PrincipalEngineer,ProductDevelopmentEngineering
Neural analysis suggests this role is
optimal for mid candidates.
“Principal Engineer, Product Development Engineering at Sandisk. Skills: NAND wafer level and Package Qualification tests setup/eFA/Action, Electrical failure analysis, DPPM reduction, NAND flash operation, Controller debug and testing. Responsible for technology DPPM reduction to meet all product spec. Responsible for NAND wafer level and Package Qualification tests setup/eFA/Action”
What You'll Achieve.
technology DPPM reduction to meet all product spec
Industry & Context.
Excellent problem-solving and analytical skills; root cause analysis of failures; electrical failure analysis
Willingness to travel abroad for short periods
What They're Looking For.
Must Have
Bachelor degree or higher in electronic, microelectronics, electrical engineering, communication or related discipline, Minimum 2 years semiconductor experience, Programming experience, preferably Python and Perl tester language, An understanding of MMC, SATA, USB or PCIE controller protocols and architectures - including datasheet specs, timings, etc., A basic background in NAND flash operation, including data sheet knowledge of specifications and timings, etc., Experience with NAND and/or Controller debug and testing
Nice to Have
3D NAND production experience, and also EFA/PFA experience, Experience in Automatic Test Equipment platforms code development (for example, Advantest, Verigy/Agilent 93000, Credence, LTX, Teradyne, etc.)
What You'll Do.
Responsible for technology DPPM reduction to meet all product spec
Responsible for NAND wafer level and Package Qualification tests setup/eFA/Action
Develop screen/stress countermeasure based on root cause analysis of failures
Providing correct test condition for the memory product and generate defined test flow for volume testing
Performing deep electrical failure analysis during new product development and ramping phase
Shoot failures from both wafer level and package level
Create analysis report based on FA finding and define the action plans
Monitor wafer and package level and DPPM pareto for miscellaneous product lines
Work with FAB/device to improve and fine tune the fab process for DPPM reduction
How You'll Work.
Team & Collaboration
communication with stockholders (Device engineer, Design engineers, Fab product engineer, etc.)
Communication Scope
The ability to clearly communicate and document findings
Full Job Description
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Responsible for technology DPPM reduction to meet all product spec. Responsible for NAND wafer level and Package Qualification tests setup/eFA/Action Plan; Develop screen/stress countermeasure based on root cause analysis of failures. Providing correct test condition for the memory product and generate defined test flow for volume testing needs; Performing deep electrical failure analysis during new product development and ramping phase. Shoot failures from both wafer level and package level. Create analysis report based on FA finding and define the action plans after communication with stockholders (Device engineer, Design engineers, Fab product engineer, etc.) Monitor wafer and package level and DPPM pareto for miscellaneous product lines. Work with FAB/device to improve and fine tune the fab process for DPPM reduction. ## Qualifications Bachelor degree or higher in electronic, mic
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