Analog Devices

semiconductor

PrincipalEngineer,PhysicalDesign

$0–0k Bangalore, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Lead candidates.

The Brief

“Principal Engineer, Physical Design at Analog Devices. Skills: Physical Design, SoC Tapeouts, Scripting, Signoff Methodologies. Lead RTL-to-GDSII execution. Drive synthesis, floorplanning, placement, CTS, routing, signoff”

What You'll Achieve.

Achieve predictable tapeouts; Ensure first-pass silicon success; High design reliability; Meet aggressive tapeout schedules; Enable power-efficient architectures

Industry & Context.

semiconductor
Eligibility Requirements

Travel: Yes, 10% of the time, Export licensing review process may apply

What They're Looking For.

Must Have

12+ years in physical design, successful tapeouts of complex, high-performance SoCs, advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below), full-chip physical design, floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, full signoff methodologies, TCL, Python, scripting, driving automation, partnering with CAD teams, flow enhancements, collaboration with RTL, DFT, packaging, product, and system teams, align on design, test, and manufacturing goals

What You'll Do.

Lead RTL-to-GDSII execution

Achieve predictable tapeouts

physical signoff strategy

Ensure first-pass silicon success

Establish and enforce DRC/LVS closure

Lead physical verification

Champion low-power design strategies

How You'll Work.

Team & Collaboration

Partnered with RTL, DFT, packaging, and system teams; Collaborated with CAD teams; Cross-functional influence; Collaboration with RTL, DFT, packaging, product, and system teams

Communication Scope

Excellent communication skills; Operate effectively in global, cross-functional environments

Process & Methodology

Lead end-to-end RTL-to-GDSII execution for a given SoC program, Achieve predictable tapeouts, Meet aggressive tapeout schedules

Full Job Description

**About Analog Devices** Analog Devices, Inc. (NASDAQ: [_ADI_](https://finance.yahoo.com/quote/ADI/?ltr=1)) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at [_www.analog.com_](https://www.analog.com/en.html) and on [_LinkedIn_](https://www.linkedin.com/company/analog-devices) and [_X_](https://x.com/ADI_News). **Key Responsibilities** * Lead end-to-end RTL-to-GDSII execution for a given SoC program, driving synthesis, floorplanning, placement, CTS, routing, and signoff to achieve predictable tapeouts. * Owned timing, power, and physical signoff strategy, including STA, SI, IR/EM analysis, ensuring first-pass silicon success and high design reliability. * Established and enforced DRC/LVS closure methodologies, led physical verification, and streamlined ECO flows to meet aggressive tapeout schedules. * Partnered with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability goals across the product lifecycle. * Defined and deployed automated design methodologies using TCL, Python, and Perl; collaborated with CAD teams to improve flow efficiency and scalability. * Championed low-power design strategies (UPF/CPF), enabling power-efficient architectures aligned with product requirements. **Position Requirements** * **Education** : B.Tech/M.Tech (or higher) in Electrical/Electronics Engineering or related field. * **Experience:** 12+ years in physical design with a proven track record of successful tapeouts of complex, high-performance SoCs across advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below).

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