Principal Engineer
PrincipalEngineer-IPVerification
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“Principal Engineer - IP Verification at Principal Engineer. Skills: IP Verification, Verification Methodologies, HVLs, HDLs. Evaluate verification methodologies. Deploy verification methodologies”
What You'll Achieve.
delivering the first pass success; ensure ‘Zero Defect’ IPs/SubSystems
Industry & Context.
address the verification challenges
What They're Looking For.
Must Have
IP / Sub-system verification, multimillion Gate and complex Design, multiple clocks, Testbench development, Testplan development, functional verification, performance aspects, Features traceability, microcontroller architecture, ARM cores, protocols like AHB/AMBA, AXI, Memory (Flash, SRAM, DDR), memory controllers, HVLs like (UVM/SV/C++), HDLs (Verilog/VHDL), PLI/DPI, simulators (NCSim/VCS/ModelSim/Questa), end to end IP verification project cycle, Testbench Strategies, TB development, simulation debugs, formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner, regression management
Nice to Have
automotive Graphics / Vision accelerators, Slow and High Speed Serial IP controllers, Networking protocols like Ethernet, drive verification methodologies, pre silicon validationulation
What You'll Do.
Evaluate verification methodologies
Deploy verification methodologies
Ensure quality adherence
Analyze existing processes
Implement process improvements
Build technological innovations
Influence technological innovations
Work as part of a team
How You'll Work.
Team & Collaboration
working with experienced and motivated team; working with Systems, Design, DFT, Mixed Signal; working with local/remote teams; work well as part of a team both locally; work with remote or multi-site teams
Process & Methodology
IP verification project cycle
Full Job Description
**_Digital IP Verification Engineers [10 to 15 yrs exp]_** **_Job Opportunity:_** Seeking highly motivated, energetic, team-oriented Individual contributor willing to take the challenge of delivering the first pass success of complex Vision / Image Processing IPs using the latest advanced verification languages and methodology. The person would be working with experienced and motivated team of Systems, Design, DFT, Mixed Signal and other local/remote teams to address the verification challenges in the context of the IP, SubSystem, and overall system, through the use of simulation, hardware modeling, formal verification and active participation in pre/post silicon validation. **_Key Responsibilities_** * Evaluate and deploy the evolving verification methodologies to handle increasingly complex IP/SubSystem designs within aggressive, market-driven schedules. * Own and ensure quality adherence during all stages of the project cycle. Ability to carry out a thorough analysis of existing processes, recommend and implement process improvements to ensure ‘Zero Defect’ IPs/SubSystems. * Building and Influencing technological innovations for self and in team environment** _._** * Hands on and ability to work well as part of a team both locally, and with remote or multi-site teams. **_Key Skills_** * Self starter with 10-15 years of experience on IP / Sub-system verification on multimillion Gate and complex Design with multiple clocks with minimal supervision * Testbench and Testplan development to ensure thorough functional verification, and performance aspects of the IP along with Features traceability. * Experience in microcontroller architecture working with ARM cores, protocols like AHB/AMBA, AXI, Memory (Flash, SRAM,DDR) and memory controllers * Experience in domains like automotive Graphics / Vision accelerators, Slow and High Speed Serial IP controllers, Networking protocols like Ethernet, would be an added advantage * Must have experience and strong working knowledge
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