PrincipalEngineerDFT

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. # Responsibilities will include, but are not limited to: * Own DFT implementation, including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for mixed signal SOC’s/ designs. * Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints. * Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams. * Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure. * Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff. * Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up. * Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis. * Partner with CAD and methodology teams to define, improve, and standardize DFT flows across Analog-Mixed Signal SoC programs. # Required Experience * Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field. * 10+ years of proven experience in SoC design, DFT, or implementation for sophisticated digital ASICs or SoCs. * Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts. # Candidates for this position will have: * Support pattern failures post silicon, ATE testing failure debug. * Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT,