Renesas Electronics
Tech / AI / Software
PrincipalEngineer,AutomatedDerivatives
“Principal Engineer, Automated Derivatives at Renesas Electronics. Skills: AI-Augmented RTL & Architecture, Intelligent Verification, Rapid Physical Implementation. Lead the end-to-end delivery of derivative SoCs. Build an AI-augmented "Silicon Factory"”
What You'll Achieve.
Achieve ultra-fast turnaround times; Reduce the number of "RTL-to-GDS" iterations; Hit aggressive power targets; Slash simulation time and compute costs; Achieve 10x faster convergence
Industry & Context.
Bridge the gap between architectural intent and GDSII; Reduce the number of "RTL-to-GDS" iterations; Hit aggressive power targets; Slash simulation time and compute costs; Achieve 10x faster convergence
Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations.
What They're Looking For.
Must Have
Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, 12–15 years of professional experience in the semiconductor industry, SystemVerilog for RTL design, UVM for functional verification, Solid understanding of Synthesis, P&R, and STA (Static Timing Analysis), Expert Python skills, Experience using Tcl/Python to extract "features" from simulation logs and implementation reports to train predictive models, Mastery of Git, Mastery of CI/CD pipelines (Jenkins/GitLab)
Nice to Have
AI-augmented "Silicon Factory" development, Machine learning to bridge the gap between architectural intent and GDSII, AI to predict physical outcomes during RTL coding, Automate the verification of design variants, ML-based predictors to evaluate RTL code for timing and congestion bottlenecks before synthesis, Develop scripts and Generative AI prompts to automate the creation of RTL wrappers, memory maps, and bus interconnects for design variants, Employ AI to identify redundant logic or clock-gating opportunities, Build AI-driven verification environments that automatically adjust constraints and coverage goals when a design derivative is instantiated, Use ML to prioritize test cases that are most likely to fail based on historical RTL changes, Deploy pattern-recognition models to identify "bug-prone" modules in the RTL based on complexity metrics and previous tape-out data, Use AI to automatically generate floorplan constraints and timing assertions from the design spec, Using AI to "reuse" placement and routing solutions from parent designs
What You'll Do.
Lead the end-to-end delivery of derivative SoCs
Build an AI-augmented "Silicon Factory"
Use machine learning to bridge the gap between architectural intent and GDSII
Achieve ultra-fast turnaround times
Evaluate RTL code for timing and congestion bottlenecks before synthesis
Automate the creation of RTL wrappers
and bus interconnects for design variants
Identify redundant logic or clock-gating opportunities
Build AI-driven verification environments
Prioritize test cases that are most likely to fail
Identify "bug-prone" modules in the RTL
Ensure a "zero-friction" path from RTL to Physical Design
Drive the physical implementation of derivatives
Reuse placement and routing solutions from parent designs
How You'll Work.
Team & Collaboration
Ensure a "zero-friction" path from RTL to Physical Design; Come together as a team in the office
Process & Methodology
Lead the end-to-end delivery
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