Micron Technology
Technology
PrincipalEngineer,ASICPreSiliconValidation(HAPSPrototypingulation)
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“Principal Engineer, ASIC Pre Silicon Validation (HAPS Prototypingulation) at Micron Technology. Skills: HAPS Prototyping, FPGA, SoC. Perform Xilinx FPGA Flow. Perform Vivado Flow”
Industry & Context.
root-cause skills
What They're Looking For.
Must Have
12+ years Processor based SoC, Hands-on HAPS implementation experience, Verilog Coding skills, Xilinx FPGA Vivado Flow, FPGA Debug Skills, Xilinx FPGA debug using Chipscope flow, Strong root-cause skills, Processor based SoC prototyping, Emulation using C/FW/AE Flow, SOC C based simulations, debug using VCS, HAPS80 is MUST to have
Nice to Have
Thorough Knowledge of HAPS, Protocompiler Flow, Xilinx Ultrascale FPGA, Vivado Flow, PCIe/NVME/LPDDR/ONFI Architecture, Knowledge of industry standard interfaces, ONFI, AXI is an advantage, Hands on HAPS 100 is most preferred
What You'll Do.
Perform Xilinx FPGA Flow
Perform Protocompiler Tool flow
Ownership of SOC deployment on HAPS
Identify FW implementation
Review SoC Verification plan
Create PCIe/LPDDR/ONFI Validation plan
Understand PCIe/LPDDR/ONFI Validation plan
Perform Processor based SoC prototyping
Perform Processor based SoC Emulation
Run SOC C based simulations
Work with overseas teams
Debug using Xilinx FPGA Vivado Flow
How You'll Work.
Team & Collaboration
Design/SOC C/FW teams; SOC C teams; AE teams; FW teams; overseas teams
Communication Scope
written communication; oral communication
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **__Job responsibilities At Glance:__** * _Complete HANDS On Xilinx FPGA Flow, Vivado Flow and Protocompiler Tool flow is Essential to Have_ * _Overall ownership of complete SOC deployment on Pre Silicon platforms like HAPS_ * _Get along with Design/SOC C/FW teams to identify actual FW implementation and plan/perform validation accordingly_ * _Review SoC Verification plan for PCIe/LPDDR/ONFI sub system and Create/understand PCIe/LPDDR/ONFI Validation plan with SOC C, AE, FW teams_ * _Develop understanding on SoC and perform Processor based SoC prototyping and Emulation using C/FW/AE Flow_ * _Should be able to run SOC C based simulations for test case understanding and debug using VCS_ * _Hands on HAPS 100 is most preferred, Hands on HAPS80 is MUST to have_ * _Work with overseas teams for PCIe/LP bring-up/debug_ * _Should be writing the Verilog RTL when required, should be able to debug using Xilinx FPGA Vivado Flow_ ** _Proficiency in FPGA Debug Skills_** * _Must have practical experience with Xilinx FPGA debug using Chipscope flow_ * _Strong root-cause skills across hardware, RTL layers_ ** __Job Qualifications__** * _Bachelors/Masters or equivalent experience in Engineering_ * _Thorough Knowledge of HAPS, Protocompiler Flow, Xilinx Ultrascale FPGA, Vivado Flow would be preferred._ * _Good understanding on any of PCIe/NVME/LPDDR/ONFI Architecture_ * _Minimum 12 + years of Processor based SoC, and hands-on HAPS implementation experience_ * _Good To Have - Knowledge of industry standard interfaces, such as ONFI, AXI is an advantage_ * _Strong Verilog Coding skills_ * _Proven experience in scripting languages such as Python / Perl / TCL_ * _Good written and oral co
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