Micron Technology
Technology
PrincipalEngineer-ASICPhysicalDesign
Neural analysis suggests this role is
optimal for Senior candidates.
“Principal Engineer - ASIC Physical Design at Micron Technology. Skills: Physical Design, STA Timing Closure, IR Analysis, DRC/LVS/ERC. Work on processors. Work on controller architectures”
Industry & Context.
Analytical skills; Problem-solving skills
What They're Looking For.
Must Have
15 years physical design implementation, 15 years IR experience, APR flow development, PPA analysis, STA closure at block, STA closure at Full Chip, Experience in Advanced process technology nodes, Experience with Ansys Redhawk-SC, Experience with Cadence layout tools, Hands on work experience in Physical verification closure, Experience in closing all the IR issues, Fundamentals of digital electronics, Fundamentals of microprocessors, Manage team independently, English language proficiency, Good collaboration skills, Good interpersonal skills, Good analytical skills, Good Problem-solving skills, Ownership, Commitment, Time management, Bachelor’s or Masters in electronics, Bachelor’s or Masters in computer architecture
Nice to Have
Strong verbal communication skills, Cadence PnR tools, Formal verification experience, Digital electronics experience, Microprocessors experience
What You'll Do.
Work on controller architectures
Block level low power aware floorplanning
Block level placement
Block level clock tree synthesis
Block level RC extraction
Block level STA timing closure
Block level IR analysis
Block level DRC/LVS/ERC
Block level tape out activities
STA closure at Full Chip
Close all the IR issues within the block
Close all the IR issues within Full chip
How You'll Work.
Team & Collaboration
Sub-system partitions closure
Communication Scope
English language proficiency
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.** # **_Role:_** The team member will typically work on processors, controller architectures or ASICs for Enterprise SSD Group. Should be proficient in block level low power aware floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tape out activities. Requirements * **Minimum of 15 years** of hands-on physical design implementation/IR/EM experience along with APR flow development and PPA analysis * STA closure at block & Full Chip * Experience in Advanced process technology nodes (5nm/3nm preferred) * Experience with Ansys **Redhawk-SC** tool * Experience with Cadence layout tools (**Innovus, Tempus** , etc..) * Hands on work experience in Physical verification closure (DRC/LVS/Antenna) with **Caliber tool** * Experience in closing all the IR issues within the block & Full chip based on feedback * Should be strong in fundamentals of digital electronics and microprocessors * Should have very good analytical skills * Should be able to manage team independently for sub-system partitions closure deliverables * Required soft skills – English language proficiency, Good collaboration and interpersonal skills. Good analytical and Problem-solving skills along with strong ownership, commitment and time management. * Bachel
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