Sandisk
Data Storage
PrincipalEngineer,ASICDevelopmentEngineering(Mixed-SignalIPLayout)
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“Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout) at Sandisk. Skills: Analog/High Speed DDR IO IC layout design, TSMC 3nm layout development, DRC/ERC/LVS/EMIR/PERC debugging, Custom layout design for Analog and IO circuits, CMOS and FinFET technologies. Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts”
What You'll Achieve.
ensuring high performance and manufacturability; meet design specifications
Industry & Context.
Excellent problem-solving skills
What They're Looking For.
Must Have
8-12 years of experience in Analog/High Speed DDR IO IC layout design, Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics, Hands-on experience with custom layout design for Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, High speed DDR IOs, Familiarity with custom digital layout (i. e. high speed logic paths), Knowledge of signal integrity issues (i. e. clock/data routes, differential routing, shielding), understanding of analog/IO design principles, including circuit performance and parasitic effects, Aware of layout techniques to mitigate ESD, latch-up issues, Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below, Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating, Experience with layout optimization for power, performance, and area (PPA) metrics, Excellent problem-solving skills and attention to detail, Effective communication and teamwork abilities
Nice to Have
Any prior AI knowledge/experience which can improve Layout development effort and QoR is a big plus, Knowledge of scripting languages (e. g. , Skill, TCL and SVRF) for automation tasks
What You'll Do.
Develop and optimize MSIP IC layouts in TSMC 3nm
ensuring high performance and manufacturability
Collaborate with design engineers to understand design requirements and translate them into precise layouts
EMIR and PERC issues independently
Work closely with the physical design team to integrate custom blocks into the overall chip design
Identify and resolve layout-related issues
providing creative solutions to meet design specifications
Conduct design reviews and provide technical feedback to improve layout practices and methodologies
Stay up-to-date with industry trends
and technologies to continuously enhance layout processes
How You'll Work.
Team & Collaboration
Collaborate with design engineers; Work closely with the physical design team; Provide technical feedback to improve layout practices and methodologies
Communication Scope
Effective communication
Full Job Description
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: * Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability. * Collaborate with design engineers to understand design requirements and translate them into precise layouts. * Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. * Work closely with the physical design team to integrate custom blocks into the overall chip design. * Identify and resolve layout-related issues, providing creative solutions to meet design specifications. * Conduct design reviews and provide technical feedback to im
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