Sandisk
Technology
PrincipalEngineer,ASICDevelopmentEngineering(FrontEndCAD-RTLIntegration,Lint,CDC)
Neural analysis suggests this role is
optimal for mid candidates.
“Principal Engineer, ASIC Development Engineering (Front End CAD -RTL Integration, Lint, CDC) at Sandisk. Skills: RTL Integration & Assembly, LINT Methodology, CDC (Clock Domain Crossing) Verification, Flow Automation & Infrastructure, Scripting & Automation. Develop and maintain robust RTL integration flows, including IP stitching, hierarchical assembly, and top-level SoC integration methodologies. Architect and maintain comprehensive RTL linting flows. Define and enforce CDC verification method”
What You'll Achieve.
Deliver best-in-class products with best-in-class quality and productivity. Accelerate design closure. Enable architecture exploration and design trade-off analysis.
Industry & Context.
system design; debugging
B. Tech / M. Tech / MS in VLSI Design, Electrical Engineering, Computer Engineering, or a related field (or equivalent industry experience).
What They're Looking For.
Must Have
~10 years of experience in front-end ASIC design, RTL integration, CAD, or methodology roles. Understanding of RTL design principles, including coding styles, synthesizability, design hierarchy, and design-for-verification best practices. Hands-on experience with RTL linting tools and methodologies. Expertise in clock and reset domain crossing verification and signoff. Proven experience with RTL and gate-level ECO methodologies. Experience with early Power, Performance, and Area (PPA) estimation tools and flows at the RTL level. Demonstrated ability to architect, develop, and deploy end-to-end front-end CAD flows for multi-million gate SoC designs. Working knowledge of industry-standard front-end tools. Proficiency in scripting and automation using TCL, Python, Perl, and/or Shell scripting.
What You'll Do.
Develop and maintain robust RTL integration flows, including IP stitching, hierarchical assembly, and top-level SoC integration methodologies.
Architect and maintain comprehensive RTL linting flows.
Define and enforce CDC verification methodologies.
Own and evolve RDC verification flows.
Develop and support RTL and netlist ECO methodologies.
Implement and maintain early Power, Performance, and Area (PPA) estimation flows on RTL.
Develop scripts, automation frameworks, and regression infrastructure.
Drive correct-by-construction and shift-left approaches.
Lead tool evaluation, qualification, and deployment for front-end CAD work.
How You'll Work.
Team & Collaboration
Work closely with RTL designers, verification engineers, synthesis teams, and physical design teams to identify recurring issues and introduce automation, checks, and best practices.
Full Job Description
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. About the Role SanDisk's ASIC team builds state-of-the-art memory controllers that power world-class NAND Flash products used globally at massive scale. The Design Enablement team enables the Technology, Methodology, and Flows to ASIC design teams to deliver best-in-class products. As the Front End CAD/Methodology Engineer, you will play a pivotal role in developing and delivering robust RTL design methodologies on cutting-edge technology nodes, enabling best-in-class quality and productivity. This role is ideal for a seasoned front-end methodology leader who enjoys solving complex RTL integration challenges, working closely with design teams, and driving innovation across flows, tools, and automation. Key Responsibilities * RTL Integration & Assembly: Develop and maintain robust RTL integration flows, including IP stitching, hierarchical assembly, and top-level SoC integration metho
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