Renesas Electronics
Tech / AI / Software
PrincipalDigitalDesignEngineer(f/m/d)
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“Principal Digital Design Engineer (f/m/d) at Renesas Electronics. Skills: digital IC design, SoC design, RTL development, Verilog/SystemVerilog, SoC architecture, low-power design, silicon tape-outs. Define digital architecture for complex mixed-signal SoCs (power management, wireless power, connectivity). Lead design and integration of digital subsystems: control logic, FSMs, datapaths, embedded microcontroller subsystems, register maps, and bus architectures (AHB/APB or equivalent)”
What You'll Achieve.
direct influence over digital architecture decisions, design methodology, and product direction for next-generation power management and connectivity SoCs; proven track record of silicon delivery; successful silicon tape-outs; Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure.
Industry & Context.
What They're Looking For.
Must Have
MSc or PhD in Electrical Engineering or a related discipline, 10+ years of experience in digital IC and SoC design, Expert-level RTL design skills in Verilog/SystemVerilog, background in SoC architecture, integration, synthesis, and timing closure, Solid knowledge of low-power design techniques, clock domain crossing (CDC), reset strategies, and design-for-test (DFT), Hands-on experience with industry-standard EDA tools (Synopsys, Cadence, or equivalent), Multiple successful silicon tape-outs as a lead or senior contributor, Fluent English communication skills
Nice to Have
Experience with mixed-signal or power IC design (BCD process, wireless power), Familiarity with embedded CPU subsystems (ARM Cortex-M or equivalent), Exposure to UVM-based verification environments, Scripting proficiency in Python or Tcl, Experience in distributed or cross-site engineering teams, Prior technical ownership at block or chip level
What You'll Do.
Define digital architecture for complex mixed-signal SoCs (power management
Lead design and integration of digital subsystems: control logic
embedded microcontroller subsystems
and bus architectures (AHB/APB or equivalent)
Own RTL development end-to-end
from micro-architecture specification through to silicon
Define and drive low-power strategies including clock gating
power domain partitioning
Collaborate with physical design teams on synthesis
Work closely with analog/mixed-signal teams on AMS interfaces
Partner with verification teams on coverage-driven verification (UVM)
Support silicon bring-up
and product validation
Author and review micro-architecture specifications and design guidelines
Define and enforce RTL coding standards
Contribute to IP reuse strategy
How You'll Work.
Team & Collaboration
Collaborate with physical design teams; Work closely with analog/mixed-signal teams; Partner with verification teams; Experience in distributed or cross-site engineering teams; Collaborative, international engineering environment
Communication Scope
Fluent English communication skills
Full Job Description
About the Role Renesas is seeking a Principal Digital Design Engineer to join our SoC development team in Zurich. This is a senior technical leadership position with direct influence over digital architecture decisions, design methodology, and product direction for next-generation power management and connectivity SoCs. The role demands deep expertise in digital IC design, a proven track record of silicon delivery, and the ability to operate effectively across engineering disciplines and organisational boundaries. Key Responsibilities Architecture & Design * Define digital architecture for complex mixed-signal SoCs (power management, wireless power, connectivity) * Lead design and integration of digital subsystems: control logic, FSMs, datapaths, embedded microcontroller subsystems, register maps, and bus architectures (AHB/APB or equivalent) * Own RTL development end-to-end, from micro-architecture specification through to silicon Low-Power & Physical Implementation * Define and drive low-power strategies including clock gating, power domain partitioning, and UPF flows * Collaborate with physical design teams on synthesis, timing closure, and PPA optimisation Cross-Functional Collaboration * Work closely with analog/mixed-signal teams on AMS interfaces * Partner with verification teams on coverage-driven verification (UVM) * Support silicon bring-up, debug, and product validation Technical Leadership * Author and review micro-architecture specifications and design guidelines * Define and enforce RTL coding standards * Mentor junior and mid-level engineers * Contribute to IP reuse strategy, design methodology, and product roadmap ## Qualifications Required Qualifications * MSc or PhD in Electrical Engineering or a related discipline * 10+ years of experience in digital IC and SoC design * Expert-level RTL design skills in Verilog/SystemVerilog * Strong background in SoC architecture, integration, synthesis, and timing closure * Solid knowledge of low-power design te
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