Astera Labs

AI infrastructure

PrincipalDigitalDesignEngineer

$185–230k San Jose, California, United States
The Brief

“Principal Digital Design Engineer at Astera Labs. Skills: micro-architecture, front-end circuit design, RTL, synthesis, IP integration, block-level verification, high performance network controllers, communication/interface protocols, PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, front end design expertise, timing closure, GLS, DFT, UVM based design verification, Silicon bring-up and debug expertise. developing micro-architecture and implementation of the front-end circuit”

Industry & Context.

AI infrastructure
Eligibility Requirements

Authorized to work in the US and start immediately

What They're Looking For.

Must Have

academic and technical background in electrical engineering, A Bachelor’s degree in EE is required, +8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications, Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision, Entrepreneurial, open-mind behavior and can-do attitude, Think and act fast with the customer in mind!, Authorized to work in the US and start immediately, Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc., Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc., Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production, Experience with Synopsys and/or Cadence digital design tools/flows, Good knowledge of design for test (DFT), stuck-at and transition scan test insertion, Familiarity with UVM based design verification, Silicon bring-up and debug expertise, Small-geometry CMOS (≤28nm) design

Nice to Have

A Master’s degree is preferred, Firmware development with C-language, scripting with Python or other equivalent programming languages, Development/support for PCIe or Ethernet Switch products

What You'll Do.

developing micro-architecture and implementation of the front-end circuit design

and block-level verification for high performance network controllers

Full chip or block level ownership from architecture to GDS

driving multiple complex designs to production

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