PowerIntegrityCo-DesignEngineer

Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphics company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to address sophisticated challenges across diverse industries. The Silicon Codesign Group (SCG) sits at the intersection of architecture, silicon, systems, and manufacturing- where deep engineering judgment drives real-world product performance at scale. SCG is evolving for an AI-enabled engineering environment, prioritizing how engineers think, reason, and complete tasks alongside advanced tools- not just narrow specialization. The SCG ArchDesign team is hiring a Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specs, and feeding silicon findings back into the next generation's design. Success in this role requires strong systems thinking and becoming comfortable with ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. **What you will be doing:** * Define product-level voltage noise targets, drive them to closure, and sign them off at shipment. * Architect voltage noise mitigation across the full stack - silicon, package, board, platform - and lead the codesign tradeoffs between them. * Co-design noise features with Speed/Power/Reliability, circuit, power-arch, ASIC, and platform teams. You're the connective tissue across the codesign web. * Build and lead the Sim-to-Si correlation methodology for voltage noise. * Model and prototype next-gen noise features - transient sense, droop response, mitigation IP. * Lead show-stopper noise bugs during bringup. * Drive architecture-level codesign tradeoffs across V/F ↔ Power ↔ Noise ↔ Reliability ↔ Thermal