NVIDIA
Artificial Intelligence, Graphics, Silicon
Post-SiliconValidationandMethodologyEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Post-Silicon Validation and Methodology Engineer at NVIDIA. Skills: Post-Silicon Validation, Methodology Engineering, AI assisted validation, Lab Automation, HW/SW Debugging. Own bring-up, validation, qualification, tuning, and productization plans for next-generation silicon. Partner across architecture, build, firmware, and software teams to define requirements for power management and clocking features”
What You'll Achieve.
Find issues before software is production-ready; Reduce the time from observation to root-cause hypothesis; Shift post-silicon coverage left; Raise velocity across programs; Close HW/SW interaction issues under schedule pressure; Increase bring-up velocity or quality through process redesign
Industry & Context.
Lead root-cause analysis on the hardest HW/SW interaction issues; Reason across the HW/SW boundary under real lab constraints; Identify where current processes break and redesign them
What They're Looking For.
Must Have
BS or MS in Electrical or Computer Engineering (or equivalent experience), 5+ years in silicon bring-up, validation, debug, or productization, Deep fundamentals across digital development, microarchitecture, timing, clocking, power, noise, and control systems, Ability to reason across the HW/SW boundary under real lab constraints, Hands-on lab proficiency: oscilloscopes, logic analyzers, power analyzers, Programming and scripting proficiency: Python, C/C++, Experience building lab automation or test infrastructure that other specialists adopt and depend on, Proficiency in the use of AI tools to accelerate silicon validation work
Nice to Have
Hardware proof of crafting: debug infrastructure you built in the lab, characterization methodologies adopted across programs, build DFT feature specs or in-system test suites you developed, or margin test flows that caught issues before production, Proficiency in bring-up experience with GPU/SoC architecture, Experience crafting or scaling in-system test and DFT features for production silicon, Familiarity with fault models, DPPM, and RAS, Concrete examples of redesigning how a team debugs in the lab — faster triage, smarter hypothesis trees, automated measurement reporting — and the resulting increase in bring-up velocity or quality
What You'll Do.
and productization plans for next-generation silicon
Partner across architecture
and software teams to define requirements for power management and clocking features
Drive coverage from pre-silicon through production
Build and deploy AI assisted lab workflows
Automate bring-up telemetry and silicon measurement data evaluation
Provide anomaly detection on regression results and debug-triage tooling
Build the test infrastructure
characterization methodologies
and bring-up playbooks
Lead root-cause analysis on the hardest HW/SW interaction issues
Identify where current processes break and redesign them: bring-up sequencing
regression frameworks
How You'll Work.
Team & Collaboration
Partner across architecture, build, firmware, and software teams; Collaborate with other specialists on lab automation and test infrastructure
Process & Methodology
Develop and own productization plans, Manage schedule pressure during issue resolution
Full Job Description
Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphic company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to tackle complex challenges across diverse industries. The problems that break late in a silicon program almost always break here first — at the boundary where architecture, design, firmware, and silicon meet reality in the lab. NVIDIA's Silicon Co-Design Group has an end-to-end view that almost no team anywhere can claim: from early architecture through bring-up to product release, across GPU, SoC, and CPU programs spanning Datacenter, Gaming, Robotics, Automotive, and Embedded. We are looking for a hardware engineer who builds the methods, test infrastructure, and coverage strategies that find issues before software is production-ready — and who rewires the team's workflow when the old approach isn't fast enough. **What you will be doing:** * Own bring-up, validation, qualification, tuning, and productization plans for next-generation silicon — from first power-on through PVT sign-off. * Partner across architecture, build, firmware, and software teams to define requirements for power management and clocking features, then drive coverage from pre-silicon through production. * Build and deploy AI assisted lab workflows. These workflows automate bring-up telemetry and silicon measurement data evaluation. They provide anomaly detection on regression results and debug-triage tooling. This tooling reduces the time from observation to root-cause hypothesis. The team runs these tools during every bring-up, not as occasional scripts. * Build the test infrastructure, characterization methodologies, and bring-up playbooks that shift post-silicon coverage left and raise velocity across programs. * Lead root-cause analysis on the hardest HW/SW interaction issues — with the measurement field, instrumenta
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