Intel Foundry Services

semiconductor

PhysicalVerificationEngineer

$129–245k Phoenix, Arizona, United States; Santa Clara, California, United States; Hillsboro, Oregon, United States FULL TIME Remote Friendly
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Experienced Hire candidates.

The Brief

“Physical Verification Engineer at Intel Foundry Services. Skills: Physical Verification, layout verification, parasitic extraction, advanced CMOS processes, EDA tools. Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges. Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations”

What You'll Achieve.

ensure successful customer tape-outs; drive quality improvements in design kits; deliver comprehensive technical guidance on advanced verification methodologies; streamline customer design workflows; enhance verification productivity; Direct impact on national security through advanced semiconductor verification solutions

Industry & Context.

semiconductor
Problems you'll solve

analytical problem-solving skills for complex physical verification challenges

Eligibility Requirements

US Citizenship required, Ability to obtain a US Government Security Clearance, Position of Trust

What They're Looking For.

Must Have

US Citizenship required, Ability to obtain a US Government Security Clearance, Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study, 3+ years of experience with advanced CMOS processes (22nm and below), 3+ years of combined experience in layout verification and parasitic extraction EDA tools, 3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting. )

Nice to Have

Active US Government Security Clearance with a minimum of Secret level, Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study, Hands-on experience in one or more areas ( LVS, DRC, ERC, PERC), Experience in parasitic extraction tools i. e. StarRC, Quantus, or xACT EDA tools, Experience with major layout editing EDA tools and flows such as ICV, Calibre and Pegasus EDA tools, Rule deck coding experience in ICV, Calibre or Pegasus EDA tools, Experience in providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work, Customer facing experience

What You'll Do.

Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges

Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations

Create application notes

comprehensive documentation

and deliver technical training presentations to customers and internal teams

Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs

Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies

Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)

Provide technical direction on layout verification methodologies including DRC

and PERC implementations

Drive methodology improvements to streamline customer design workflows and enhance verification productivity

Deliver customer-facing technical support with focus on physical verification challenges and solutions

Support customers through complex verification issues and advanced process technology adoption

Ensure maximum customer satisfaction through expert guidance and responsive technical support

How You'll Work.

Team & Collaboration

Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution

Communication Scope

Effective communication skills

Process & Methodology

effectively manage multiple complex tasks

Full Job Description

# **Job Details:** ## Job Description: **About Intel Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape-outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies. **Key Responsibilities** **Physical Verification Support & Issue Resolution** * Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges * Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on physical and layout design rules and extraction issue resolution * Resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations **Technical Content Development & Training** * Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams * Drive quality improvements in design kits and documentation to remove barriers to successful customer design tape-outs * Develop best practice guidelines for physical verification flows and methodologies across advanced process technologies **Verification Methodology Leaders

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