Company
PhysicalDesignEngineer
Neural analysis suggests this role is
optimal for Mid+ candidates.
“Physical Design Engineer. Skills: Physical Design, EDA tools, Timing closure. Physical design for NVIDIA GPU. Physical design for Mobile chips”
What You'll Achieve.
Ensure high quality of design implementation
Industry & Context.
Troubleshoot design issues; Troubleshoot flow issues
What They're Looking For.
Must Have
BS in Engineering or Science or equivalent experience, Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk), Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes, 2+ years of experience in above areas
Nice to Have
MS in Engineering or Science, Knowledge in FinFET technology, circuit design, and package design, Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre), Proficiency in Perl, Python, TCL and Makefile scripts
What You'll Do.
Physical design for NVIDIA GPU
Physical design for Mobile chips
Full chip floorplanning
Signal integrity analysis
Physical verification
Troubleshoot design issues
Troubleshoot flow issues
Apply proactive intervention
How You'll Work.
Team & Collaboration
Collaborate with RTL designers; Collaborate with DFT designers; Collaborate with Circuit designers
Full Job Description
We are now looking for VLSI Physical Design Engineers in Hsinchu office, Taiwan. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit. **What you’ll be doing:** * A role in physical design for NVIDIA GPU and Mobile chips. * Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention. * Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation. **What we need to see:** * BS in Engineering or Science or equivalent experience * Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus) or Ansys (Redhawk) * Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes * 2+ years of experience in above areas **Ways to stand out from the crowd:** * MS in Engineering or Science * Knowledge in FinFET technology, circuit design, and package design * Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre) * Proficiency in Perl, Python, TCL and Makefile scripts
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