NVIDIA
Networking Silicon
PhysicalDesignEngineer
Neural analysis suggests this role is
optimal for Senior candidates.
“Physical Design Engineer at NVIDIA. Skills: Physical design, Timing closure, VLSI. Lead physical design implementation. Work at partition level”
What You'll Achieve.
Deliver highest throughput; Deliver lowest latency
Industry & Context.
Analytical skills; Debugging skills
What They're Looking For.
Must Have
3+ years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology, Able to assist in design flow development and debugging, including application of ML/AI solutions, Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions, analytical and debugging skills
Nice to Have
Proficiency using Python, Perl, Tcl, Make scripting is helpful
What You'll Do.
Lead physical design implementation
Work at partition level
Establish design methodologies
Perform chip floorplan
Distribute power/clock
Perform chip assembly
Achieve timing closure
Perform trial synthesis
Analyze power and noise
Perform physical verification
How You'll Work.
Team & Collaboration
Member of a team; Great teammate
Full Job Description
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company. **What you 'll be doing:** * You will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets. * Work will be at the partition level. * As a member of a team, you will participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure. * Daily work involves all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification. **What we need to see:** * BSEE / MSEE or equivalent experience. * 3+ years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology. * Able to assist in design flow development and debugging, including application of ML/AI solutions. *
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