Analog Devices, Inc.
semiconductor
PhysicalDesignDirector
“Physical Design Director at Analog Devices, Inc.. Skills: Physical Design, SoC Implementation, PPA Optimization, Signoff Methodologies. Direct end-to-end RTL-to-GDSII execution. Drive synthesis, floorplanning, placement, CTS, routing, and signoff”
What You'll Achieve.
predictable tapeouts; first-pass silicon success; high design reliability; meet aggressive tapeout schedules; achieve predictable tapeouts; achieve QoR (PPA) targets; improve efficiency; ensure execution predictability; enable power-efficient architectures
Industry & Context.
PPA optimization; congestion management; advanced routing methodologies; library strategy; DRC/LVS closure; ECO flows; risk management
10% travel, export licensing review process
What They're Looking For.
Must Have
15+ years in physical design, proven track record of leadership, successful tapeouts of complex, high-performance SoCs, advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm and below), Deep expertise in full-chip physical design, floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, full signoff methodologies, command of STA, constraint development, signoff closure (timing, SI, IR), first-pass silicon success, predictable delivery, define, drive, and scale design methodologies and flows, achieve QoR (PPA) targets, improve efficiency, ensure execution predictability, Solid understanding of device, interconnect, and circuit challenges in advanced/Udsm nodes, experience navigating scaling complexities, Proficiency in TCL, Python, or similar scripting, driving automation, partnering with CAD teams for flow enhancements, collaboration with RTL, DFT, packaging, product, and system teams, align on design, test, and manufacturing goals, Excellent communication skills, ability to influence executive stakeholders, operate effectively in global, cross-functional environments
Nice to Have
low power design strategies (UPF/CPF)
What You'll Do.
Direct end-to-end RTL-to-GDSII execution
and physical signoff strategy
Ensure first-pass silicon success
Drive PPA optimization
Establish and enforce DRC/LVS closure methodologies
Lead physical verification
and manufacturability goals
Build and scale high-performing physical design teams
Mentor senior engineers and technical leads
Foster a culture of execution excellence
Define and deploy automated design methodologies
Collaborate with CAD teams
Improve flow efficiency and scalability
Deliver high-complexity designs on advanced nodes
and cross-functional dependencies
Champion low-power design strategies
How You'll Work.
Team & Collaboration
Partnered with RTL, DFT, packaging, and system teams; Collaborated with CAD teams; Cross-functional influence; Collaboration with RTL, DFT, packaging, product, and system teams
Communication Scope
Excellent communication skills; ability to influence executive stakeholders; operate effectively in global, cross-functional environments
Process & Methodology
managing risk, schedules, cross-functional dependencies
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