SpaceX
NewGraduateEngineer,ASICDesign(Starshield)
Neural analysis suggests this role is
optimal for Entry candidates.
“New Graduate Engineer, ASIC Design (Starshield) at SpaceX. Skills: ASIC Design, FPGA Design, RTL Implementation. Design digital ASICs. Design FPGAs”
What You'll Achieve.
Go from design to demo; Achieve operational capability
Industry & Context.
Solving problems; Clock domain crossings; Power optimization
Work long hours, Work weekends, Willing to travel, TS-SCI clearance, Drug testing
What They're Looking For.
Must Have
Bachelor's degree in EE, CE, or CS, Graduating in 2026 or 2027, 1+ years RTL implementation experience, 1+ years FPGA/ASIC development experience
Nice to Have
Experience with clock domain crossings, Experience with power optimization, Experience developing complex ASICs, Experience with multicore CPU subsystem design, Experience with standard bus protocols, Experience with embedded processors, Experience with high speed design, Experience with low power design, Scripting skills, Experience with HDL simulators, Experience with HDL Lint tools, Experience with FPGA tools
What You'll Do.
Evaluate architectural trade-offs
Derive specifications
Define micro-architecture
Deliver verified design
Provide timing constraints
Support physical implementation
Participate in silicon bring-up
Participate in validation
Assist in test equipment development
How You'll Work.
Team & Collaboration
Highly collaborative environment; Work with modem/DSP engineers; Work with RFIC engineers; Work with verification team; Work with physical implementation team
Full Job Description
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. NEW GRADUATE ENGINEER, ASIC DESIGN (STARSHIELD) Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U. S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. RESPONSIBILITIES: Design digital ASICs and/or FPGAs for Starshield projects. Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains. Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design. Work closely with verification team to ensure all aspects of the design are covered and verified. Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check). Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab mea
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