Micron Technology

Technology

MTSASICArchitect

₹65–100L ~AI est. Bengaluru, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“MTS ASIC Architect at Micron Technology. Skills: ASIC Architecture, DRAM Architecture, Silicon Architecture. Lead architectural trade off analysis. Influence functional partitioning”

What You'll Achieve.

Deliver scalable, reliable, high-performance memory solutions; Ensure high-quality execution; Ensure first-silicon success

Industry & Context.

Technology
Problems you'll solve

Architectural trade off analysis; PPA evaluation; IO timing considerations; Scalability paths; Mitigation strategies

What They're Looking For.

Must Have

Bachelor's degree or higher, 15 years of experience, Worked on uArch/Arch of SoC or Subsystems, Leading technical definition across peers & design teams, High speed digital logic design experience, Familiarity with HIP/Analog blocks usage & integration trade-offs, DRAM Architecture knowledge, Deep understanding of architectural tradeoffs, Demonstrated technical leadership, Demonstrated reviews, Demonstrated mentoring, Work independently, Self-learning, Driving own goals, Ability to work in ambiguity, Make reasonable assumptions, Validate assumptions through definition cycle, Take critical feedback, Drive resolutions with an open mind, Guide micro-architects/designers, Perform review of uArch, RTL, test plans and test coverage

Nice to Have

Master's or PhD degree (or equivalent experience), Experience on multi-die interfaces is a plus, Experience collaborating across multiple technical domains, Experience engaging with customers, Experience engaging with ecosystem partners, Experience engaging with industry standards organizations, Demonstrated technical leadership across multiple projects or product generations, Familiarity with system-level tradeoffs

What You'll Do.

Lead architectural trade off analysis

Influence functional partitioning

Drive architectural analysis

Perform micro‑architectural reviews

Perform design reviews

Perform verification reviews

Perform coverage reviews

Guide mitigation strategies

Influence cross-functional decisions

Serve as technical mentor

Serve as architectural authority

Elevate technical rigor

Elevate design quality

Guide micro-architects

Perform review of uArch

Perform review of RTL

Perform review of test plans

Perform review of test coverage

How You'll Work.

Team & Collaboration

Collaborating with design; Collaborating with product; Collaborating with systems; Collaborating with ecosystem partners; Cross-functional decisions; Execution teams

Communication Scope

Clear reasoning; Data-driven analysis

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Role Overview** The **DRAM ASIC Architecture team** defines silicon level architectures that extend and differentiate the value of Micron’s DRAM products. The team works across technology generations and product lines, collaborating closely with design, product, systems, and ecosystem partners to deliver scalable, reliable, and high-performance memory solutions aligned with customer and market needs. As an **Member of Technical Staff** , you will provide senior level architectural leadership for ASIC and logic-based DRAM solutions that emphasize **high bandwidth, energy efficiency, scalability, and reliability**. This role spans **near term product execution** and **long term technology direction** , with architectural ownership over decisions that impact bandwidth density, latency, RAS, and system observability. **Key Responsibilities** * Lead architectural trade off analysis across DRAM silicon, ASIC logic, packaging constraints, and system integration considerations - accounting for power delivery, thermals, signal integrity, and form factor limitations. * Influence functional partitioning and interface definition across DRAM devices and logic die to optimize performance, power, and scalability * Drive architectural analysis including PPA evaluation, IO timing considerations, and scalability paths for next generation DRAM products. * Perform micro‑architectural, RTL, and design reviews, along with verification and coverage reviews, to ensure high‑quality execution and first‑silicon success & guide mitigation strategies in collaboration with design and validation teams. * Influence cross‑functional decisions through clear reasoning, data‑driven analysis, and

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