MatX

Technology

Micro-ArchitectandRTLDesigner

$200–300k ~AI est. Mountain View, California, United States FULL TIME Remote Friendly
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Micro-Architect and RTL Designer at MatX. Skills: Micro-architecture, RTL Design, Silicon design. Contribute to silicon architecture-to-design methodology. Own subsystem or subsets”

What You'll Achieve.

Deliver performant silicon; Deliver functionally accurate silicon

Industry & Context.

Technology
Problems you'll solve

Performance closure; Coverage closure

Eligibility Requirements

Authorized to work in US, U.S. export controls

What They're Looking For.

Must Have

4 years or more experience with SystemVerilog, 4 years or more experience with Python, 4 years or more experience with C/C++, Production-proven experience on silicon micro-architecture, Production-proven experience on silicon design concepts, Experience with testing designs, Hands-on experience with design synthesis, Hands-on experience with design lint

Nice to Have

Familiarity with verification platforms is a plus, Familiarity with emulation platforms is a plus, Experience with high speed I/O IP is a plus, Experience with logic that focuses on moving data is a plus, Experience with logic that focuses on storing data is a plus, Experience with logic that focuses on managing data is a plus

What You'll Do.

Contribute to silicon architecture-to-design methodology

Own subsystem or subsets

Own chip-level silicon design deliverables

Plan reviews on micro-architecture

Plan reviews on design specifications

Plan reviews on execution progress

Plan reviews on area closure

Plan reviews on timing closure

Drive reviews on micro-architecture

Drive reviews on design specifications

Drive reviews on execution progress

Drive reviews on area closure

Drive reviews on timing closure

Work closely with verification co-owners

Work closely with DFT co-owners

Work closely with physical design co-owners

Deliver best-in-class performance-power-area results

How You'll Work.

Team & Collaboration

Work closely with verification; Work closely with DFT; Work closely with physical design

Full Job Description

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results Who You Are Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon 4 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals Hands-on experience with design synthesis, desig

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