Micron Technology

Semiconductor

MemberofTechnicalStaff,AIEngineering

$350–650k ~AI est. Boise, Idaho, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Member of Technical Staff, AI Engineering at Micron Technology. Skills: AI Engineering, GPU Performance, Distributed Training, GenAI. Architect custom model training. Fine-tune custom models”

Industry & Context.

Semiconductor
Problems you'll solve

Root cause analysis

What They're Looking For.

Must Have

10+ years GPU architecture experience, 5+ years performance optimization, 5+ years parallel computing, 5+ years low-level systems, C++ programming, GPGPU frameworks, Scalable ML systems experience, Distributed training experience, Model parallelism experience, End-to-end automation experience, LLMs proficiency, Prompt engineering, Tool/function calling, Chain-of-thought reasoning, PEFT methods fine-tuning, LoRA fine-tuning, QLoRA fine-tuning, vLLM inference optimization, TensorRT-LLM inference optimization, GenAI applications development, AI agents development, CI/CD experience, Cloud-native tools experience, Git experience, Jenkins experience, Docker experience, Kubernetes experience, Bachelor's degree in Computer Science, Bachelor's degree in Statistics, Master's degree in Computer Science, Master's degree in Statistics

Nice to Have

Ph.D. in Computer Science, Ph.D. in Statistics, HPC job schedulers experience, Kubernetes orchestration experience, Ray experience, Kubeflow experience, CUDA programming expertise, Triton kernels expertise, C++ extensions for PyTorch, Multi-agent systems design, Computer vision experience, Signal processing experience

What You'll Do.

Architect custom model training

Fine-tune custom models

Optimize training throughput

Optimize memory efficiency

Design autonomous AI Agents

Develop autonomous AI Agents

Automate manufacturing workflows

Analyze complex workloads

Profile complex workloads

Write high-performance kernels

Optimize high-performance kernels

Unlock hardware capabilities

Collaborate with Hardware Architects

Define features for GPUs

Design performance regression suites

Catch performance degradations

How You'll Work.

Team & Collaboration

Partner with data scientists; Partner with engineers; Partner with hardware architects

Process & Methodology

CI/CD, Agile

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Smart Manufacturing and AI team builds advanced machine learning, GenAI, and Agentic AI solutions that directly power Micron’s manufacturing advantage. We work at the intersection of cutting‑edge AI and real‑world production systems, turning massive data and compute into measurable impact. If you enjoy solving hard problems at scale and seeing your work drive silicon to market, this is the team for you! This role is critical to how we train, optimize, and deploy large‑scale AI systems on modern GPU platforms. As a GPU Performance Engineer, you will push the limits of multi‑GPU and distributed training, shape next‑generation AI workloads, and partner closely with data scientists, engineers, and hardware architects. Your work will directly influence performance, cost, and speed across Micron’s AI‑powered manufacturing stack. **Responsibilities:** * Architect and complete large-scale custom model training and fine-tuning jobs (SFT, RLHF) on multi-node, multi-GPU clusters. * Optimize training throughput and memory efficiency using distributed training strategies (FSDP, DeepSpeed, Megatron-LM) and mixed-precision techniques (FP16/BF16). * Design and develop autonomous AI Agents capable of multi-step reasoning, planning, and tool execution to automate complex manufacturing workflows. * Analyze and profile complex workloads (e.g., LLM training, Rendering pipelines) to identify bottlenecks in compute, memory bandwidth, and latency. * Write and optimize high-performance kernels using CUDA, HIP, or custom assembly (PTX/SASS) to unlock hardware capabilities. * Collaborate with Hardware Architects to define features for next-generation GPUs based on workload characteriza

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