Micron Technology
Semiconductor
LeadPrincipalEngineer,LayoutDesign
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“Lead Principal Engineer, Layout Design at Micron Technology. Skills: Layout Design, Physical Verification, Tapeout Signoff. Lead layout build. Lead physical realization”
What You'll Achieve.
Drive cost; Drive quality; Drive reliability; Drive time-to-market; Drive customer happiness
Industry & Context.
Problem-solving; Debug skills
What They're Looking For.
Must Have
10+ years experience Semiconductor industry, Bachelor's degree in EE/CE or related, Understanding of CMOS devices, Hands-on custom IC layout experience, Experience with physical verification tools, Comprehensive understanding of reliability checks, Experience leading technical execution, Experience delivering tapeouts, Proficiency in scripting/automation
Nice to Have
Master's Degree or PhD, In-depth knowledge advanced-node layout, In-depth knowledge memory/storage trends, Excellent problem-solving skills, Excellent debug skills, Ability to prioritize multiple tasks
What You'll Do.
Lead physical realization
Interpret device specifications
Interpret circuit specifications
Implement custom layout solutions
Develop hierarchical layouts
Build block floorplans
Build top-level floorplans
Optimize routing resources
Optimize signal integrity
Optimize power delivery
Optimize manufacturability
Optimize layout for die size
Optimize layout for area efficiency
Optimize layout for matching
Optimize layout for coupling
Optimize layout for noise
Optimize layout for timing
Produce layout collateral
Produce layout documentation
Run physical verification flows
Debug physical verification flows
Ensure closure using industry tools
Perform parasitic extraction
Assess impact on timing
Assess impact on power
Assess impact on noise
Assess impact on functionality
Resolve layout issues
Drive standard physical build practices
Maintain layout documentation
Participate in continuing education
Solicit feedback from groups
Innovate for future memory generations
Optimize layout-centric solutions
Improve methodologies
Lead resource planning
Lead tapeout schedules
Serve as contact for layout implementation
Serve as contact for physical verification
Serve as contact for PEX/signoff
Serve as contact for integration issues
Track closure of achievements
Coordinate ECO execution
Communicate implementation status
How You'll Work.
Team & Collaboration
Collaborate with Circuit Designers; Collaborate with Verification Engineers; Collaborate with CAD/Methodology experts; Collaborate with Process Integrators; Collaborate with Product Engineers; Collaborate with Test/Probe specialists; Collaborate with Assembly professionals; Collaborate with Marketing strategists
Process & Methodology
Resource planning, Priority management, Schedule management, Tapeout schedule management, ECO execution management
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Lead Principal Engineer, Layout Design at Micron, you will be at the forefront of developing groundbreaking memory solutions! This role is an outstanding opportunity to lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts. You will collaborate with a world-class team of Circuit Designers, Verification Engineers, CAD/Methodology experts, Process Integrators, Product Engineers, Test/Probe specialists, Assembly professionals, and Marketing strategists. Together, we will drive cost, quality, reliability, time-to-market, and customer happiness through outstanding layout and build. ## Key Responsibilities * Lead the layout build and physical realization of new memory products. * Interpret device and circuit specifications to implement custom layout solutions meeting PPA (power, performance, area) and reliability targets. * Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools. * Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability. * Optimize layout for critical metrics such as die size/area efficiency, matching, coupling/noise, and timing. * Produce layout collateral and documentation for cross-team integration. ## Physical Verification and Tapeout Signoff * Run and debug physical verification flows and ensure closure using industry tools. * Perform parasitic extraction and work with circuit designers to assess impact on timing, power, noise, and functionality. * Resolve layout issues related to signal integrity, coupling/c
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