NVIDIA
LeadPerformanceModelingArchitect,CPUFabricandLLC
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“Lead Performance Modeling Architect, CPU Fabric and LLC at NVIDIA. Skills: Performance Modeling, Computer Architecture, Silicon Architecture, Technical Leadership, Cache Coherency Protocols, Large-Scale Simulators, Statistical Analysis. Guiding the performance architecture team. Acting as the primary architect for performance models covering next-generation cache hierarchies and I/O coherent interconnects”
What You'll Achieve.
Ensuring our silicon delivers industry-leading performance-per-watt; Meeting project achievements with modeling approaches; Accelerate the build cycle
Industry & Context.
Resolving complex performance bottlenecks and trade-offs; Ability to explain how architectural decisions affect total cost of ownership or safety margins
What They're Looking For.
Must Have
Master’s or Ph. D. in Computer Engineering or a related field (or equivalent experience), 8+ years of experience in high-performance silicon architecture, Extensive experience managing technical teams or complex projects in the field of performance modeling or computer architecture, Proficiency in cache coherency protocols (e.g., AMBA CHI, MESI), Proficiency in memory sub-systems, Proficiency in high-speed interconnect fabric build, Significant experience building and architecting large-scale simulators in C++ or SystemC, with a focus on modularity and simulation speed, Track record of using statistical analysis to validate model accuracy against RTL or silicon, Ability to explain complex performance "cliffs" to executive collaborators
Nice to Have
Full-Stack Performance Experience: Seen the entire lifecycle of an interconnect—from a whiteboard sketch and C++ model to RTL integration and post-silicon performance tuning, Standardization Influence: Active participation in industry bodies (e.g., CXL Consortium, Arm ecosystem committees) or a history of published architectural research, Scalability Expertise: Proven record of addressing the outstanding challenges of both low-latency, safety-critical clusters and massive, high-bandwidth mesh networks for cloud-scale deployments, Critical Thinking: Ability to explain not just how a system works, but also how architectural decisions affect the total cost of ownership for data centers or safety margins in automotive
What You'll Do.
Guiding the performance architecture team
Acting as the primary architect for performance models covering next-generation cache hierarchies and I/O coherent interconnects
Ensuring models scale from Automotive to Data Center platforms
Guiding a group of top-performing engineers
Converting high-level product requirements into actionable architectural specifications
Ensuring silicon delivers industry-leading performance-per-watt
Balancing individual technical contributions with team mentorship and multi-functional strategy
Defining the long-term vision for the modeling infrastructure
Choosing between cycle-accurate
and stochastic modeling approaches
Leading a team of modeling engineers
Offering in-depth technical mentorship
Conducting code/architecture reviews
Encouraging a culture of rigorous data-driven decision-making
Acting as the primary liaison between Architecture
Resolving complex performance bottlenecks and trade-offs
Driving the adoption of advanced modeling methodologies
Accelerating the build cycle
Allocating simulation workloads and engineering efforts across several simultaneous projects
How You'll Work.
Team & Collaboration
Guiding a group of top-performing engineers; Balancing individual technical contributions with team mentorship; Acting as the primary liaison between Architecture, RTL Build, and Software teams; Collaborating with executive collaborators; Collaborating with industry bodies (e.g., CXL Consortium, Arm ecosystem committees)
Communication Scope
Ability to explain complex performance "cliffs" to executive collaborators
Process & Methodology
Managing complex projects in the field of performance modeling or computer architecture, Allocating simulation workloads and engineering efforts across several simultaneous projects
Full Job Description
We are seeking a Lead Performance Modeling Engineer to guide our performance architecture team. You will act as the primary architect for performance models covering next-generation cache hierarchies and I/O coherent interconnects. These models will scale from Automotive to Data Center platforms. You will guide a group of top-performing engineers, converting high-level product requirements into actionable architectural specifications and ensuring our silicon delivers industry-leading performance-per-watt. As a technical lead, you will balance individual technical contributions with team mentorship and multi-functional strategy. **What you 'll be doing:** * Defining the long-term vision for our modeling infrastructure, choosing between cycle-accurate, analytical, and stochastic modeling approaches to meet project achievements. * Leading a team of modeling engineers, offering in-depth technical mentorship, conducting code/architecture reviews, and encouraging a culture of rigorous data-driven decision-making. * Act as the primary liaison between Architecture, RTL Build, and Software teams to resolve complex performance bottlenecks and trade-offs. * Drive the adoption of advanced modeling methodologies (e.g., hybrid emulation/simulation, AI-based performance optimization) to accelerate the build cycle. * Allocate simulation workloads and engineering efforts across several simultaneous projects in the automotive and data center sectors. **What we need to see:** * A Master’s or Ph.D. in Computer Engineering or a related field (or equivalent experience), with 8+ years of experience in high-performance silicon architecture. * Extensive experience managing technical teams or complex projects in the field of performance modeling or computer architecture. * Proficiency in cache coherency protocols (e.g., AMBA CHI, MESI), memory sub-systems, and high-speed interconnect fabric build. * Significant experience building and architecting large-scale simulators in C++ or SystemC, wi
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