Micron Technology
Technology
LayoutEngineer-DPG-LPDDR
Neural analysis suggests this role is
optimal for Senior candidates.
“Layout Engineer-DPG-LPDDR at Micron Technology. Skills: Analog Layout, Process technologies, Circuit integration. Layout and integration of analog blocks. Ensure low-noise performance”
What You'll Achieve.
First-silicon success
Industry & Context.
Parasitic optimization; Noise mitigation; Performance risk resolution
What They're Looking For.
Must Have
B. E. or equivalent experience, M. Tech in VLSI Build, Microelectronics, or Electronics Engineering
Nice to Have
AI/ML knowledge as a benefit
What You'll Do.
Layout and integration of analog blocks
Ensure low-noise performance
Ensure high reliability
Ensure operation across PVT corners
Apply device physics expertise
Drive high-quality layout implementation
Complete high-speed layout techniques
Focus on impedance control
Focus on skew matching
Focus on crosstalk mitigation
Work with circuit designers
Enable layout-aware build
Identify parasitic risks
Identify performance risks
Lead post-layout optimization
Lead sign-off activities
Provide technical mentorship
Conduct design reviews
Contribute to guidelines
Support data-driven optimization
Support layout automation
Improve debug workflows
Improve correlation workflows
How You'll Work.
Team & Collaboration
Circuit designers; Architects
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join our ambitious team in Hyderabad as a Senior Analog Layout Engineer-DPG-LPDDR and contribute to our mission of transforming information into intelligence. You will be responsible for the layout and integration of key analog blocks, ensuring outstanding performance and reliability across advanced process technologies. * Take responsibility for the layout and integration of essential analog blocks, guaranteeing low-noise performance, high reliability, and strong operation across PVT corners for advanced process technologies. * Apply strong device physics expertise to drive high-quality layout implementation, including transistor matching strategies, well and substrate engineering, parasitic optimization, and EM/ESD reliability considerations. * Complete and review high-speed layout techniques for sensitive analog and mixed-signal paths, focusing on impedance control, skew matching, shielding, isolation, and crosstalk mitigation. * Work closely with circuit designers and architects to enable layout-aware build, proactively identifying and resolving parasitic, noise, and performance risks early in the design cycle. * Lead post-layout optimization and sign-off activities, including DRC/LVS, EM/IR analysis, and correlation of post-layout simulations with silicon or lab data. * Provide technical mentorship and conduct design reviews for complex blocks, contributing to guidelines, quality improvement, and first-silicon success. * Leverage AI/ML knowledge as a benefit to support data-driven optimization, layout automation initiatives, and improved debug and correlation workflows. **Education** * B.E. or equivalent experience in Electronics, Electronics & Communication
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