Astera Labs

Technology

JuniorPhysicalDesignEngineer

$180–270k ~AI est. Haifa, Israel FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Entry candidates.

The Brief

“Junior Physical Design Engineer at Astera Labs. Skills: Physical design, RTL-to-GDS flow, Signoff flows. Establish local execution culture. Establish technical standards”

What You'll Achieve.

Meet performance targets; Meet power targets; Meet area targets

Industry & Context.

Technology
Problems you'll solve

Solve complex challenges

What They're Looking For.

Must Have

Bachelor’s degree in Electrical Engineering, RTL-to-GDS flow understanding, Floorplanning exposure, Placement exposure, Routing exposure, Familiarity with 7nm process, Basic signoff methodologies experience, Basic STA experience, Basic LEC experience, Basic DRC experience, Basic EMIR analysis experience, Working knowledge of TCL scripting, Working knowledge of Python scripting

Nice to Have

Full-chip level implementation experience, Full-chip level integration experience, Power analysis knowledge, Noise analysis knowledge, DFT requirements familiarity, Experience with Synopsys Fusion Compiler, Experience with Synopsys ICC2, Experience with Cadence Innovus, High-speed interface designs background, Connectivity protocols background

What You'll Do.

Establish local execution culture

Establish technical standards

Take responsibility for physical implementation

Perform Floorplanning

Perform Place & Route

Perform Clock-Tree Synthesis

Own macro-level implementation

Perform floorplanning

Perform complex routing

Drive design integrity

Perform Timing signoff

Perform Physical Verification

Perform Reliability analysis

Ensure first-pass silicon success

Apply Logic Equivalence Checking

Guarantee design correctness

Define Backend methodologies

Refine Backend methodologies

Improve tool automation

Navigate challenges of advanced process nodes

Navigate high-speed connectivity challenges

Leverage scripting for automation

Leverage automation for environment

How You'll Work.

Team & Collaboration

Cross-functional collaboration; Work with Architecture teams; Work with Design teams; Work with DFT teams

Full Job Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is y

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